aldavis
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Posts: 4
Flint, Michigan
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The pressing need is for a multi-tool environment, with about 10 tools interacting. Only 2 of them are simulators.
VHDL has the concept of an "entity" which has one or more "architectures". In verilog, these concepts are combined into a "module". The "entity" specifies the interface, much like a function prototype in C. The "architecture" implements it. The body of an "architecture" is equivalent to the body of a "module".
The important feature is that there can be several "architectures" and a language supported way to specify it.
In simulation, one use of separate architectures might be a structural and behavioral model of the same entity, or possibly a fast model and an accurate model, or a nice model that guarantees convergence, used to start a homotopy to an accurate model that might not be so well behaved.
entity FOOBAR is .... end entity
architecture yellow of FOOBAR is .... end architecture
architecture green of FOOBAR is ....
architecture red of FOOBAR is ....
architecture blue of FOOBAR is ....
I can refer to FOOBAR, and have which one automatically selected somehow, or I can refer to FOOBAR(blue) or something like that.
I suppose it could be done in Verilog with the preprocessor:
`ifdef yellow module FOOBAR .... `else `ifdef green module FOOBAR ....
... `endif `endif
but we want to be able to select more than one, perhaps to compare one to another.
Another approach could be multiple modules with a naming convention
module FOOBAR_yellow ....
module FOOBAR_green ....
.. and we could have a "proprietary" way to map and select.
But we don't want proprietary. We want to support industry standards, and make the best use of them. We have existing tools in Verilog and would like to stick with it. Our user community has indicated a strong preference for Verilog over VHDL.
So ..
Is there an official language specified way to do this? (I can't find it.)
Is there a precedent for naming conventions or something like that?
Is there a better way?
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