hi -

I have a non-hidden-state reset DFF (D is always tied high).

I'd like it to come up in zero state, and not go high until the first rising edge of vclk1.

What I've done below (set a flag @ initial_step) does not work.

Does anybody know how to solve this problem?

thanks

Gabe

module d_ff_r(vclk1, vrst, q, qb);
input vclk1, vrst;
output q, qb;
electrical vclk1, vrst, q, qb;
parameter real vlogic_high = 1.8;
parameter real vlogic_low = 0;
parameter real vtrans = 1;
parameter real tdel = 1n from [0:inf);
parameter real trise = 1n from (0:inf);
parameter real tfall = 1n from (0:inf);
integer now1, out1, x;

  analog begin

     now1=0;
     x=1;

     @ ( initial_step ) begin
           x=0;
     now1=1;
     end
     
     @ (cross(V(vclk1)-vtrans,+1)) begin
           now1=1;
     x=1;
     end
     
     @ (cross(V(vrst)-vtrans,-1)) begin
           now1=1;
     x=1;
     end      
     
     y1=((V(vrst)>vtrans) && (x==1));      
     
     out1=idt(0,y1,now1);
     
       V(q) <+ transition( out1 ? vlogic_high:vlogic_low,tdel, trise, tfall );
       V(qb) <+ vlogic_low + vlogic_high - V(q);
     end
endmodule

thanks Ken!