By dimensional analysis you're missing a current in the denominator, and the only current in the problem is the charge pump source. I can't see any reason for the 10.

Do PLL designs these days still use an external cap?

M.G.Rajan

Every PLL I've designed or worked on this millenium  has had an internal cap.  Usually (always, I think) gate-cap of a native NFET, from 50pF to 2nF (that one was called the 'solar panel').

Actuall leakage is typically very small.  I've watched the frequency remain roughly constant for seconds after the PFD/qpump is turned off.

If leakage is present, the loop has to correct for it.  So the amount of leakage-induced jitter will be a function of the loop bandwidth, the filter-cap size, the VCO gain. Leakage will lower the control voltage by whatever charge it drains off the filter-cap between up/dwn pulses.  Bigger cap, less delta-V.  Lower K0, less delta-F.  Higher bandwidth, less time for leakage to discharge the filter cap, less delta-V.