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yamamaya

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why variable to branch incorrectly? help!
Apr 03^rd, 2007, 12:08am

I'v written a jfet model in verilogA and simulated it in Hspice 2006.9. But I cant contribute the calculated current to the port correctly. In the model I'v used while loops and some conditional statements. I display the variable which computes the current of one port during the simulation and find it right. However when I use <+ to set the variable to the port, the simulated result is wrong. In the whole model I'v used <+ only once. I have followed the demo and such conditions do not happen. What's wrong maybe with my model?
bow!

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Geoffrey_Coram

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Re: why variable to branch incorrectly? help!
Reply #1 - Apr 3^rd, 2007, 7:37am

Did you try the JFET model available from this site? Click the Verilog-AMS on the right side of the banner at the top of this page. My suspicion would be that you mis-used <+: if you do
I(g) <+ igs;
then you are actually putting a current from the global ground to the gate. You really want to be contributing to a branch current, which is more natural, anyway:
I(g,s) <+ igs;
I(g,d) <+ igd;

I'm puzzled how you can write a model for a 3-terminal device with only one <+.

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yamamaya

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Re: why variable to branch incorrectly? help!
Reply #2 - Apr 5^th, 2007, 5:58am

Geoffrey_Coram wrote on Apr 3^rd, 2007, 7:37am:

Did you try the JFET model available from this site? �Click the Verilog-AMS on the right side of the banner at the top of this page. �My suspicion would be that you mis-used <+: if you do
I(g) <+ igs;
then you are actually putting a current from the global ground to the gate. �You really want to be contributing to a branch current, which is more natural, anyway:
I(g,s) <+ igs;
I(g,d) <+ igd;

I'm puzzled how you can write a model for a 3-terminal device with only one <+.

3x for ur helps! When I said I used <+ once, I mean I had just set I(d,s), I(g,s), and I(g,d) once. I set I(d,s)<+Id, which I calculated and verified by $display(Id), and I set I(d,s)<+ 0.0, I(g,s)<+0.0 respectively. I never used I(g) or so in branch contribution.
Something more: I had put my va file compiled in Spectrum today and simulated. I found the difference between the variable and the port current is much smaller than that of Hspice. Most of time they matched. Only in some point they are not equal but the error is about only 0.01%. So I wonder if there are little bugs in Hspice working with VerilogA?

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Geoffrey_Coram

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Re: why variable to branch incorrectly? help!
Reply #3 - Apr 5^th, 2007, 7:14am

Is it a dc-only model -- you haven't put in any charge equations yet, right?

I wouldn't immediately suspect the Verilog-A compiler. You might check your tolerances; I know GMIN can be a problem in real JFET simulations, because the actual gate current is so small that GMIN dominates. But then, you say that you have no gate current.

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yamamaya

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Re: why variable to branch incorrectly? help!
Reply #4 - Apr 5^th, 2007, 7:37am

Geoffrey_Coram wrote on Apr 5^th, 2007, 7:14am:

Is it a dc-only model -- you haven't put in any charge equations yet, right?

I wouldn't immediately suspect the Verilog-A compiler. �You might check your tolerances; I know GMIN can be a problem in real JFET simulations, because the actual gate current is so small that GMIN dominates. �But then, you say that you have no gate current.

yep, it is only for dc now.
Which tolerance do you mean? The one in the calculation in my model or the one supplied by the simulator? How can I change the tol in the simulator and test it in run time? May I give a very little gate current?

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Geoffrey_Coram

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Re: why variable to branch incorrectly? help!
Reply #5 - Apr 6^th, 2007, 3:25am

I think you control the tolerances with a .OPTION card in HSpice, eg
.OPTION RELTOL 1e-4

Note that the default RELTOL in Spice is 1e-3, which is actually larger than the 0.01% you report.

Also, when you try to compare the $display to the actual port current, how are you obtaining the port current, and are you sure you have the exact same timepoint? Eg, if you're trying to set a cursor and read the value off of a waveform displayer, there may be inaccuracies in the graphical display or the interpolation routine.

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yamamaya

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Re: why variable to branch incorrectly? help!
Reply #6 - Apr 6^th, 2007, 6:17am

I simulated only to solve the operation point, so the timepoint in the process doesnt matter. The whole circuit contains a jfet and a resistence and I just measure the current flowing through the resistence. Since I only do .op and .dc for the source, the current should be equal to the one shown by $display of the jfet, if the contribution process runs correctly. Now they are different in Hspice but similar in Spectrum.

I suspect that in the iterations exerted by the simulator, Hspice call my model for several times and it may add up all the drain current in each iteration to the last current, or someof them. I am not sure but some data hint. But I am sure every variable is set before used or quoted. There seems no chance that the previous results may affect the latter. I am confused since I can not debug the Hspice step by step.

I feel I should look into the Tol in the Hspice as you say. But .OPTION RELTOL 1e-4 cannot be used and I will check the syntax. Thank you for your attention and help. Bow!

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Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA	Re: why variable to branch incorrectly? help! Reply #7 - Apr 6^th, 2007, 12:23pm Maybe it's .OPTION RELTOL=1e-4 Depending on the compiler in your version of HSpice, you might be able to use $debug() to print values on each iteration; it takes the same arguments as $display().
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