Geoffrey_Coram wrote on Apr 3rd, 2007, 7:37am:Did you try the JFET model available from this site? Click the Verilog-AMS on the right side of the banner at the top of this page. My suspicion would be that you mis-used <+: if you do
I(g) <+ igs;
then you are actually putting a current from the global ground to the gate. You really want to be contributing to a branch current, which is more natural, anyway:
I(g,s) <+ igs;
I(g,d) <+ igd;
I'm puzzled how you can write a model for a 3-terminal device with only one <+.
3x for ur helps! When I said I used <+ once, I mean I had just set I(d,s), I(g,s), and I(g,d) once. I set I(d,s)<+Id, which I calculated and verified by $display(Id), and I set I(d,s)<+ 0.0, I(g,s)<+0.0 respectively. I never used I(g) or so in branch contribution.
Something more: I had put my va file compiled in Spectrum today and simulated. I found the difference between the variable and the port current is much smaller than that of Hspice. Most of time they matched. Only in some point they are not equal but the error is about only 0.01%. So I wonder if there are little bugs in Hspice working with VerilogA?