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sapphire Community Member Offline Posts: 37	how about digital PLL? Apr 09^th, 2007, 4:35pm The said digital PLL consists of digital controlled oscillator, time to digital converter, and digital filter, and so on. TI proposed this concept in 2005. Is this a good topic for PHD thesis? What can be exployed then? Confused.... Thanks
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adesign Community Member Offline Posts: 73	Re: how about digital PLL? Reply #1 - Apr 9^th, 2007, 8:40pm Jitter is the major issue with Digital PLL. You can research on "Controlling jitter in DPLL"
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vivkr

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Re: how about digital PLL?
Reply #2 - Apr 10^th, 2007, 2:39am

sapphire wrote on Apr 9^th, 2007, 4:35pm:

The said digital PLL consists of digital controlled oscillator, time to digital converter, and digital filter, and so on.

TI proposed this concept in 2005.

Is this a good topic for PHD thesis? What can be exployed then? Confused....

Thanks

Hi sapphire,

I am not sure if you are quite accurate with the dates and the inventors. I believe that the first ones to propose this were Motorala and they did this sometime in the early 90s or late 80s. I know this because I myself have used the concept and designed a digital PLL consisting of a digitally controlled oscillator and digital filters (no cap, charge-pump based filters) way back in 2000. And at that time, the Motorola paper was the reference. However, I don't remember exactly who wrote it. I will check and see if I can find it.

As for PhD topic, that depends on what kind of improvements you propose to bring into the field.

Regards
Vivek

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hyy95 Junior Member Offline Posts: 10	Re: how about digital PLL? Reply #3 - Apr 11^th, 2007, 4:36pm DPLL is too easy to do, the algorithm in C can be done in less than 200 lines, and logic codes in verilog can be done in less than 2000 lines. I don't know why u want to do it as a PHD thesis since it's just a basic buiding block for a digital receiver. doing so is like designing a opamp as a PHD thesis.
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fonseca.ha

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Re: how about digital PLL?
Reply #4 - Apr 12^th, 2007, 11:34am

hyy95 wrote on Apr 11^th, 2007, 4:36pm:

DPLL is too easy to do, the algorithm in C can be done in less than 200 lines, �and logic codes in verilog can be done in less than 2000 lines. I don't know why u want to do it as a PHD thesis since it's just a basic buiding block for a digital receiver. doing so is like designing a opamp �as a PHD thesis.

I totally disagree that a Digital PLL is not a good topic for phD thesis. there are many things to be investigated.
Sure you can make a Digital PLL with a few lines, like you can make an opamp with 7 transistors, but what frequency? what jitter? what bandwidth? can it compete with an analog PLL for performance? What about Digital PLLs for RF?

Noadays, to my knowladge, for example the time to digital conversion in a DPLL has a resolution comparable to the performance of an analog PLL. can you investigate how to make it better?

What about this, can you arrange a digital core that can make the BW of the transfer function from the Digital VCO to the output as high as possible while mantaining the BW of the transfer function from input to the output as low as possisble, sop that the DPLL can clean both its Digital VCO and its Input?

Regards,
H.

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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: how about digital PLL? Reply #5 - Apr 12^th, 2007, 8:44pm Key thing of thesis research: It has to be new It has to go someplace never gone before It has to be something your thesis advisor and thesis committee are interested in and receptive to. Read the last requirement very very very carefully. academic survival 101: give them what they want to hear.
Back to top	Jerry Twomey www.effectiveelectrons.com Read My Electronic Design Column Here Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical IP Logged

hyy95

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Posts: 10

Re: how about digital PLL?
Reply #6 - Apr 13^th, 2007, 10:37pm

maybe we are not talking about the same topic.
I am not talking about DPLL used for analog or RF ckts, I am talking about the digital phase lock loop in a digital receiver. So there's no digital VCO for any analog/RF use. All the performance bottle neck comes from the ADC, after the ADC, everything is digital, running on a free-running clock. Digital phased lock loop is used to track carrier offset, there are lots of algorithms to improve the performance, but comparing to other part in the digital receiver, such as channel equalization, the DPLL is much easier.
the idea of soft radio is move ADC up as high as possible, and after ADC, everything is done in the digital world.

fonseca.ha wrote on Apr 12^th, 2007, 11:34am:

hyy95 wrote on Apr 11^th, 2007, 4:36pm:

DPLL is too easy to do, the algorithm in C can be done in less than 200 lines, and logic codes in verilog can be done in less than 2000 lines. I don't know why u want to do it as a PHD thesis since it's just a basic buiding block for a digital receiver. doing so is like designing a opamp as a PHD thesis.

I totally disagree that a Digital PLL is not a good topic for phD thesis. there are many things to be investigated.
Sure you can make a Digital PLL with a few lines, like you can make an opamp with 7 transistors, but what frequency? what jitter? what bandwidth? can it compete with an analog PLL for performance? What about Digital PLLs for RF?

Noadays, to my knowladge, for example the time to digital conversion in a DPLL has a resolution comparable to the performance of an analog PLL. can you investigate how to make it better?

What about this, can you arrange a digital core that can make the BW of the transfer function from the Digital VCO to the output as high as possible while mantaining the BW of the transfer function from input to the output as low as possisble, sop that the DPLL can clean both its Digital VCO and its Input?

Regards,
H.

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buckaroo

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Posts: 8
Tsinghua Univ. PRC

Re: how about digital PLL?
Reply #7 - Apr 23^rd, 2007, 10:02am

hello
i will work on DPLL, however, i know little about it at present, i want to be an expert on the project, haha:)
i think DPLL has a bright torrow
hyy95 wrote on Apr 13^th, 2007, 10:37pm:

maybe we are not talking about the same topic.
I am not talking about DPLL used for analog or RF ckts, I am talking about the digital phase lock loop in a digital receiver. So there's no digital VCO for any analog/RF use. All the performance bottle neck comes from the ADC, after the ADC, everything is digital, running on a free-running clock. Digital phased lock loop is used to track carrier offset, there are lots of algorithms to improve the performance, �but comparing to other part in the digital receiver, such as channel equalization, the DPLL is much easier.
the idea of soft radio is move ADC up as high as possible, and after ADC, everything is done in the digital world.

fonseca.ha wrote on Apr 12^th, 2007, 11:34am:

hyy95 wrote on Apr 11^th, 2007, 4:36pm:

DPLL is too easy to do, the algorithm in C can be done in less than 200 lines, �and logic codes in verilog can be done in less than 2000 lines. I don't know why u want to do it as a PHD thesis since it's just a basic buiding block for a digital receiver. doing so is like designing a opamp �as a PHD thesis.

I totally disagree that a Digital PLL is not a good topic for phD thesis. there are many things to be investigated.
Sure you can make a Digital PLL with a few lines, like you can make an opamp with 7 transistors, but what frequency? what jitter? what bandwidth? can it compete with an analog PLL for performance? What about Digital PLLs for RF?

Noadays, to my knowladge, for example the time to digital conversion in a DPLL has a resolution comparable to the performance of an analog PLL. can you investigate how to make it better?

What about this, can you arrange a digital core that can make the BW of the transfer function from the Digital VCO to the output as high as possible while mantaining the BW of the transfer function from input to the output as low as possisble, sop that the DPLL can clean both its Digital VCO and its Input?

Regards,
H.

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