maybe we are not talking about the same topic.
I am not talking about DPLL used for analog or RF ckts, I am talking about the digital phase lock loop in a digital receiver. So there's no digital VCO for any analog/RF use. All the performance bottle neck comes from the ADC, after the ADC, everything is digital, running on a free-running clock. Digital phased lock loop is used to track carrier offset, there are lots of algorithms to improve the performance, but comparing to other part in the digital receiver, such as channel equalization, the DPLL is much easier.
the idea of soft radio is move ADC up as high as possible, and after ADC, everything is done in the digital world.
fonseca.ha wrote on Apr 12th, 2007, 11:34am:hyy95 wrote on Apr 11th, 2007, 4:36pm:DPLL is too easy to do, the algorithm in C can be done in less than 200 lines, and logic codes in verilog can be done in less than 2000 lines. I don't know why u want to do it as a PHD thesis since it's just a basic buiding block for a digital receiver. doing so is like designing a opamp as a PHD thesis.
I totally disagree that a Digital PLL is not a good topic for phD thesis. there are many things to be investigated.
Sure you can make a Digital PLL with a few lines, like you can make an opamp with 7 transistors, but what frequency? what jitter? what bandwidth? can it compete with an analog PLL for performance? What about Digital PLLs for RF?
Noadays, to my knowladge, for example the time to digital conversion in a DPLL has a resolution comparable to the performance of an analog PLL. can you investigate how to make it better?
What about this, can you arrange a digital core that can make the BW of the transfer function from the Digital VCO to the output as high as possible while mantaining the BW of the transfer function from input to the output as low as possisble, sop that the DPLL can clean both its Digital VCO and its Input?
Regards,
H.