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How to simulate reference spur of PLL ? (Read 3717 times)
ben-w
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How to simulate reference spur of PLL ?
Apr 10th, 2007, 7:25pm
 
I wrote a PLL behavioral model using Verilog-a ,but at the output of VCO,i cann't see the reference spur. I use a nonideal CP model and  do fft in calculator to see the result.Can anyone tell me why?thanks a lot.
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« Last Edit: Apr 11th, 2007, 12:25am by ben-w »  
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sheldon
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Re: How to simulate reference spur of PLL ?
Reply #1 - Apr 13th, 2007, 8:44pm
 
Ben,

There are several possibilities,
1) Is the VCO control voltage a nearly constant value without any
   noise or impulses?
   Probably a problem with the PFD, if the PFD is in its dead zone then
   there will be no reference spur. Basically, you will need to fix the PFD.
2) Does the VCO control voltage have noisy, ringing, jumps, etc.?
   The PLL may not be in lock yet. You should wait longer so that
   the PLL settles and achieves lock.
3) The VCO control line voltage is nearly constant, with impulses.
   The impulses should repeat at the reference frequency, this
   is the reference clock feeding through to the control line.
   In this case, if the fft does not show a reference spur, then
   the issue is probably in the calculation of the fft. The most
   likely problem is interpolation error, if you are using Spectre
   then you can:
   a) Use the zvcs, to re-sample the waveform and eliminate
       interpolation error.
   b) Use Ken Kundert's MATLAB function for calculating the
       phase noise, it should show the reference spur
   c) Use the four component to calculate the output frequency
       spectrum, note, you will probably need to create your own  
       Verilog-A model to implement a window function.

    Good Luck!

                                                       Best Regards,

                                                       Sheldon
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