ywguo
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Hi, Guys,
Jose Bastos adopted a current cell in his paper, "A 12-bit intrinsic accuracy high-speed CMOS DAC," JSSC 1998. The cell is proposed by Hiroshi Takakura, "A 10 bit 80 MHz glitchless CMOS D/A converter," CICC 1991. A schematic is shown in the attached pdf file.
Here MP1 is a current source biased by VB1, operating in saturation region. MP2 and MP3 are switching transistors operating in linear region, controlled by a pair of complemant digital input d and db. MP4 and MP5 are cascaded transistors isolating the output node from switching transistors. MP4 and MP5 operate in linear region, too. MP4/5 has the same dimensions with MP2/3.
Jose Bastos claimed that the series connection of switching transistor and the cascaded transistor is equivalent to a single transistor working in saturation, with a channel length twice as large.
I don't understand it. If Jose Bastos is right, what is the vth and vdsat for the equivalent transistor working in saturation region?
Best regards, Yawei
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