Hi Matt,
I want to reiterate that my experience have been with .18/.13RF processes and the .25RF should not be that much different. However, I highly recommend you go through at least these 2 docs carefully: (1) mixed signal layout design rules (2) gdsII layer usage. Both should be available off TSMC website and you (or someone in your organization) should have access to it. The design rules manual has the layout rules for dnwell. The gdsII layer usage lists out tapeout layers vs DRC/LVS purpose layers.
To answer your question:
webb0111 wrote on Apr 23rd, 2007, 9:22am:Am I to use a dnwell layer surrounded by an nwell ring, as in I only need those two layers to isolate my NMOS (no psub/pwell)?
To achieve what you are trying to do which NMOS bulk to source connection, you need to use the DNWELL layer ... no other way around it. To do so, you need to follow the layout design rules of the DNWELL. If you follow that correctly, PSUB2 and PWELL will not be needed.
webb0111 wrote on Apr 23rd, 2007, 9:22am:And for the use of PSUB2 as a trick to pass LVS, my extracted circuit (with use of PSUB2) has very similar characteristics as my schematic circuit, but is this not a true repesentation? I guess my question here is, will it be able to be fabricated or not?
The use of PSUB2 comes in handy in situation where there are multi-grounds in the design for noise isolation (eg. digital gnd vs analog ground). The grounds are routed out separately to IO pads but they may be tied off chip. Potentially, they are the same and PSUB2 provides a way to pass LVS. PSUB2 is not a tape-out layer so it will not be used to fabricate your chip. Covering an area with PSUB2 creates an artificial well for LVS but not a real well on silicon. Yes, your extracted circuit will behave the same since your extract command file is no different from LVS command file.
Hope this helps,
LL
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