Hello,

I am having a problem in tsmc025rf technology layout in Cadence.  In my schematic design there are 4-terminal transistors.  So in my analog designs, I used body-source connections for all transistors, unlike in digital design where the body is connected to either VDD or VSS.  I have been unable to determine a way to do NMOS body-source connections in layout because it is an nwell process and thus all NMOS share a p-substrate.  In PMOS this can be done by isolating the nwell for different transistors (I think).

This leads me to believe that somehow I need to isolate the p-substrates for each NMOS that does not have its source directly connected to VSS, and then connect the isolated substrates to the respective sources.  The Art of Analog Layout was a small help, but I do not understand how to apply its technique.

Any help on this topic is appreciated.  If more information is needed I will be happy to oblige.

Thanks again,

Matt

Matt, in brief, you're stuck for NMOS unless the process also has p-wells.  Check the design rule manual.

If you don't have p-wells, all NMOS bodies are the same, and so you should tie them to VSS.  The problem is that you get a body effect because Vsb is not zero, and the threshold voltage is higher.  If the source and body in a well are shorted, you add a source cap resulting from the junction of the n-well and p-substrate.  There's no free lunch.

matt,

   as YWGUO and SKAS20 said, Deep Nwell will isolate you NMOS transistors and then you can tie S and B of your NMOS together. I remember that TSMC25RF support the DNWELL by add a mask, as SKAS20 mentioned. furthermore,use DNwell NMOS transistors will make your layout area much larger than normal NMOS.

rocky

It seems that using the PSUB2 layer instead of the PWELL layer works.  Thanks everyone.

usually PSUB2 layer is the pseudo layer which differentiates between two p-substrates.
e.g., if one part of the substrate is AGND1 and other part is  AGND2, then drawing  pusb2 layer in AGND2
isolates that from AGND1.
In this case AGND1 is usual substrate and AGND2 area is isolated one.

Hi Matt,

I would first try to get hold of a process manual where they show you a cross section of the chip with different wells and the substrate.
Here, you will be able to really see whether or not it is possible to fabricate an isolated pwell at all. Generally, you need a DNWELL for
this. If not, then your design will not work when fabricated.

Generally, it is not possible to tie the bulk of NMOS devices to anything except substrate, and since this is a TSMC process, I am not
sure if you can do it otherwise, but in any case, please check the process manual.

Also, be careful to ensure that the well parasitics are modelled if you are using a source-bulk connection and not tying it to substrate.
Otherwise, your circuit will suffer from performance issues.

Regards
Vivek

Hi, Krishnap,

Sure the n-well guardring has some extent of isolation. We usually separate multiple ground in one chip using n-well guardring. But the NMOS body is still tied to ground, not source of itself. Matt's problem is to tie NMOS body to its source.


Best regards,
Yawei

Hello Matt,
I'm going to repeat some info here that have already been posted but I hope I won't do too much of that.  My experience is with TSMC .18um and 0.13 RF but I think the 0.25um is not going to be too far (if at all) from those.

To answer you questions:

(1) Yes, a triple well process is needed in order to have NMOS bulk-to-source ties.  The Deep Nwell (DNW) option at TSMC will provide the 3rd well for your needs. Notice that I wrote option because this indeed will add additional mask cost (1 mask in this case).  But in general most RF designs I've seen take advantage of the DNW option for noise isolation.  Plus, if you use TSMC's RF devices, you will have little choice but to use the DNW unless you plan to develop your own model.  On the subject of modeling, I've heard from my colleague that previously NMOS in deep well had a different characteristic vs the NMOS outside of deep nwell.  However, that's not the case now ... at least it's not in the .18um and .13um processes.  TSMC releases the same model deck for both devices.

(2) In regard to your question about LVS, the use of nwell ring and PSUB2 will break the substrate soft-tie and allow you to tie bulk to source for NMOS.  Independent of DNW usage, you can get LVS to pass with these "tricks".  Notice that I wrote tricks because they are indeed tricks to pass LVS.  PSUB2 is not a mask and nwell ring doesn't create a separate well for you.   Be very cautious when you use these.  Now, getting back to your deep nwell layout, if the layout is done correctly, there should be an nwell ring going around the edge of your DNW layer.  The nwell ring will break the substrate for you in LVS and you should not have to use PSUB2.  Connection from that point is simple. Psub inside the ring should be tied to the source of that device.  On a side note, this design style will create a very large layout. One last comment on LVS, if the .25um LVS deck is anything like the .18u/.13um deck, NMOS inside DNW vs NMOS outside DNW will get extracted with different model names.  You schematic have to reflect this to get LVS passed cleanly.

I hope I have answered your questions.

cheers,
LL