mg777
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I need to understand the IC manufacturing cost structure for a mixed-signal ASIC, details below.
(i) RF in the 50-250 MHz range (ii) ADC-DAC 12 bit @ 1 MSPS (iii) 100K digital gates + 16 KB SRAM (iv) 50 MHz clock freq (v) 32K of Flash (or E2PROM) (vi) ESD & I/O cells (vii) 16 pin TSSOP or QFN, wirebond (viii) Volume 1M up per quarter
The cost includes a production mask set, X mm wafer fab, packaging, & ATE (Iddq/Pin + scan + analog verif). Royalties for digital physical blocks need not be included here. The goal is to choose an optimal technology node - say between 90 nm, 130 nm, & 0.18 um.
I keep hearing a wafer fab cost of 10 cents per mm2 for 130 nm - is this correct, and will it be less for 0.18? Any answers or references appreciated.
M.G.Rajan
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