Designer’s Guide Community

rajdeep

Senior Member

Offline

Posts: 220
UK

Simulation of cells with VerilogA view
Apr 18^th, 2007, 11:57pm

Hi all,

Say, I have a top module named TOP. It uses three submodules A1,A2 and A3. All these modules have only no veriloga view.
They do not have symbol or schematic view. I only create a Symbol of the top module TOP.

I instantiate this TOP in a design schematic and try to run the whole system. But it fails to complete the step of netlisting
When I create symbols of the submodules A1, A2 and A3 it works fine.

Why do I need the symbol view of these A1, A2 and A3? In the hierarchy editor I use only their veriloga view. I had to create the symbol view
of the top module TOP because I had to instantiate it into another design schematic.

Is there a way out? or I have to create the symbols?

Plz help!
Rajdeep

Back to top

Design is fun, verification is a requirement.

IP Logged

Andrew Beckett

Senior Fellow

Offline

Life, don't talk to
me about Life...

Posts: 1742
Bracknell, UK

Re: Simulation of cells with VerilogA view
Reply #1 - Apr 19^th, 2007, 3:28am

If I remember rightly, you do need the symbols. That said, it's not exactly onerous to create the symbols, since they can be generated automatically from the verilog-a code.

But I may be wrong - I've not checked this recently, nor done any searches to see what the current status is (so why am I answering?).

Anyway, I wanted to make sure that you were using the automatic symbol generation (which it would ask you to do when you created the verilog-a views), and if not, why not?

Andrew.

Back to top

IP Logged

rajdeep

Senior Member

Offline

Posts: 220
UK

Re: Simulation of cells with VerilogA view
Reply #2 - Apr 19^th, 2007, 5:01am

Hi Andrew,

I've posted a reply message to one of my own queries (!!) how to generate a symbol from verilogA view.
http://www.designers-guide.org/Forum/YaBB.pl?num=1176965163
Very much, the same command you suggested.
So, currently I'm not too much worried about not having symbol view of submodules, which are in verilogA .

Thanks a lot Andrew!!

Rajdeep

Back to top

Design is fun, verification is a requirement.

IP Logged