Hello ESD guru's of the forum:

Before stating my questions, please allow me to setup the scenario:
My IO ring consists of multiple power segments with back2back diodes separating the VDD and VSS of each segment.  Each segment has at least one set of power pads (VDD and VSS).  The ESD structure of each power pad is two clamp diodes (gcNMOS and ggPMOS).  This gives a minimum of 4 clamps diodes per power segment.  The ESD structure of the IO pad falls into two catergory: (a) for analog the structures are gcNMOS and gcPMOS (b) for digital the ESD devices are part of the output driver with remaining unused devices connected s ggNMOS & ggPMOS.

An external failure analysis house performs the ESD test.  The signals are first divided into groups of power individually, gnd collectively, and IO individually.  Take the example of a ring with 2 set of power pins (VDD1, VDD2, GND1, and GND2) .  The test procedure would be as follow:
(1) +zap of all pins individually with reference to VDD1 --> check for failure
(2) -zap of all pins individually with reference to VDD1 --> check for failure
(3) +zap of all pins individually with reference to VDD2 --> check for failure
(4) -zap of all pins individually with reference to VDD2 --> check for failure
(5) +zap of all pins individually with reference to GND1+GND2 (all grounds collectively) --> check for failure
(6) -zap of all pins individually with reference to GND1+GND2 (all grounds collectively) --> check for failure
(7) +zap of all IO pin individually with reference to other IO pin individually --> check for failure
(8) -zap of all IO pin individually with reference to other IO pin individually --> check for failure

Failure is defined as high leakage and/or resistive short.

My questions:
(1) Given a test sequence, if a failure is discovered on a particular pin, does it really mean that pin failed under its own test? For example, take sequence #1 above and  a failure is reported on an IO pin (let's say signalA).  Did signalA failed when signalA was zap in reference to VDD1 or did it fail under another test (let's say VDD2 zapped in reference to VDD1)?  I have a hard picturing this.  My though is that signalA could have failed in any of the zap during the sequence.  Can someone please clear this up for me?
(2) My IO ring has a special cell that is used in a few locations.  ESD report shows failure in multiple instances of this cell but not ALL of the instances failed ESD.  An IR scan shows the location of the failure and it somewhat makes sense.  However, what really puzzle me is why some instances of this cell passed ESD.  My though is that the cell is probably marginal and I should be really looking for weakness in the IO ring construction.  What do you think?

My experience with ESD failure analysis is low and that also means I might have left out key details in posting these questions.  Please ask and I will try to provide.

thanks in advance,
LL

Thank you Stephen for your insights.  My test house check the pins after each group of test (eg. check all pins for failure after the zapping pins in reference to VDD1).  You confirmed what I was having a hard time understanding.

Yes, I agree on the second comment.  The cell is marginal and hopefully I can push it over min requirement with some internal correction.

Again thanks for your insight.  I learn a lot from your posts in this forum.

regards,
LL