SRF Tech wrote on Apr 12th, 2007, 8:54am:Dandelion,
First off, if you are attempting to debug ESD failures without actual failure analysis, you need to examine why you have determined the pin is failing.
So: first questions: Is it current leakage? Is it a functional failure? If leakage, is it leaking to Vdd or Vss? Do you see the nwell resistance in the leakage path?
If I were to put my money on your problem, its the oxide of the diff pair. You have an exposed oxide there, and the only other device/node (ignoring ESD structures themselves) is MOS diffusion isolated by nwell resistance (which, both are natural ESD protection structures in and of themselves). I imagine the nwell resistance is fairly large (i.e. >100 ohms for ESD concerns)
Assuming its the oxide, why does one pin fail and the other pass?
Lots of reason for this. First and foremost is that diode based ESD protection is highly dependent on power bussing, ground bussing and Power Clamp placement (think lots of series resistances and how they play together). You need to consider how different the power bussing and clamp location is between the pin that passes, and the apparently equivalent pin that fails. The mere fact that you have not posted the power bussing model for your ESD architecture tells me that your problem is very likely related to that, as it has been apparently ignored.
You need to look at your global ESD model, how well placed are the diodes, how well connected are they in metal to power busses, how well routed are the power busses and how well they connect to the power clamps? How well placed are the power clamps? My main point, is ESD is not about having a single great protection device that you just plug onto an IO. Desiging for ESD protection is 20% device design and 80% architecture consideration in my opinion.
I really hope this helps you out. please let me know if you have other questions.
Thanks,
Stephen
Hi Stephen,
Thanks for the help. In my ESD failure criteria, it is the lekage current.
In fact, I was waiting for another ESD test to verify if it is the NWELL resistor caused the ESD failure. Now, we have got the feedback. I think, it is an interesting ESD failure phenominon.
First, I applogize I have ignored a very important clue in my previous post. The other good pin and the failed pin is in fact the differential inputs of opa amp in the diagram.Pls see the attached diagram in this post. Also, it is 0.6um CMOS process instead of 0.5um CMOS.Sorry for the typo.
Second,for the past days, we did some other ESD test and FA analysis for our chip. We found an interesting thing. We found out the reason why the pin1 is OK while pin2 failed. We found that when we do IO to IO- ESD ZAP from the pin1 to pin2, the pin2 failed while the pin1 is OK. So that's why the pin1 is always OK while the pin2 failed. This is because we always test pin1 first and then pin2 in standard HBM test.
We carefully checked our layout and found the two nwell resistor are interleaved connected for better matching. So we think, is it because the two nwell res layout each other will form two back to back diodes, we believe this is the culpit.
Third, we have taped our another chip with the same topology with 0.5um CMOS. The same topology and same ESD strategy, the only descranpancy is the nwell resistor is replaced with poly. So we did another ESD test and this time it passed.
So we conculed that the interleaved NWELL resistor caused our ESD failure. But what I am still not clearly is what mechnism lead to this failure?
Also, I found in the test, the IO to IO- from pin1 to pin2 is always lead the pin2 failed. But the IO to IO+ from pin2 to pin1, it rarely failed. Per my understanding, these two modes should be eqvailent. Any wrong with it?
Thanks
Dandelion