hi,
I have an ESD issue I can not explain. Hope to get you ESD gurus's help.

Pls. see the attached diagram. This is the connection for the failed pin. The Pin did not pass the HBM 1500V for IO to IO- ESD ZAP. I can not understand why.

First, I doubt the gate is damaged. But the other pins which only connected the gate with same ESD protection is OK.It shows the ESD diode works well.  So I doubt the NWELL resistor and the NMOS Tr whith its drain tied to the NMELL resistor maybe the criminal.

But I can not think out what possible failure mechanisim exsist.

BTW, it is the 0.5um CMOS process. The ESD diode can stand the 4000V ESD ZAP.

Would you help me on it?

Thanks a lot
Dandelion

Dandelion,
First off, if you are attempting to debug ESD failures without actual failure analysis, you need to examine why you have determined the pin is failing.

So: first questions: Is it current leakage?  Is it a functional failure?  If leakage, is it leaking to Vdd or Vss?  Do you see the nwell resistance in the leakage path?  

If I were to put my money on your problem, its the oxide of the diff pair.  You have an exposed oxide there, and the only other device/node (ignoring ESD structures themselves) is MOS diffusion isolated by nwell resistance (which, both are natural ESD protection structures in and of themselves). I imagine the nwell resistance is fairly large (i.e. >100 ohms for ESD concerns)

Assuming its the oxide, why does one pin fail and the other pass?

Lots of reason for this. First and foremost is that diode based ESD protection is highly dependent on power bussing, ground bussing and Power Clamp placement (think lots of series resistances and how they play together).  You need to consider how different the power bussing and clamp location is between the pin that passes, and the apparently equivalent pin that fails.  The mere fact that you have not posted the power bussing model for your ESD architecture tells me that your problem is very likely related to that, as it has been apparently ignored.

You need to look at your global ESD model, how well placed are the diodes, how well connected are they in metal to power busses, how well routed are the power busses and how well they connect to the power clamps?  How well placed are the power clamps?  My main point, is ESD is not about having a single great protection device that you just plug onto an IO.  Desiging for ESD protection is 20% device design and 80% architecture consideration in my opinion.

I really hope this helps you out.  please let me know if you have other questions.
Thanks,
Stephen

SRF Tech wrote on Apr 12^th, 2007, 8:54am:


Hi Stephen,
Thanks for the help. In my ESD failure criteria, it is the lekage current.

In fact, I was waiting for another ESD test to verify if it is the NWELL resistor caused the ESD failure. Now, we have got the feedback. I think, it is an interesting ESD failure phenominon.

First, I applogize I have ignored a very important clue in my previous post. The other good pin and the failed pin is in fact the differential inputs of opa amp in the diagram.Pls see the attached diagram in this post. Also, it is 0.6um CMOS process instead of 0.5um CMOS.Sorry for the typo.

Second,for the past days, we did some other ESD test and FA analysis for our chip. We found an interesting thing. We found out the reason why the pin1 is OK while pin2 failed. We found that when we do IO to IO- ESD ZAP from the pin1 to pin2, the pin2 failed while the pin1 is OK. So that's why the pin1 is always OK while the pin2 failed. This is because we always test pin1 first and then pin2 in standard HBM test.

We carefully checked our layout and found the two nwell resistor are interleaved connected for better matching. So we think, is it because the two nwell res layout each other will form two back to back diodes,  we believe this is the culpit.

Third, we have taped our another chip with the same topology with 0.5um CMOS. The same topology and same ESD strategy, the only descranpancy is the nwell resistor is replaced with poly. So we did another ESD test and this time it passed.

So we conculed that the interleaved NWELL resistor caused our ESD failure. But what I am still not clearly is what mechnism lead to this failure?

Also, I found in the test, the IO to IO- from pin1 to pin2 is always lead the pin2 failed. But the IO to IO+ from pin2 to pin1, it rarely failed. Per my understanding, these two modes should be eqvailent. Any wrong with it?

Thanks
Dandelion

Dandelion,
  Your design is very interesting and I could probably write a book proposing possible failure mechanisms based on your topology and layout that you have just shown me.  However I will explain what is the most probable cause.

Your Nwell resistors are prone to what we call "lateral" NPN snapback.  You have a bipolar device parasitically built into your resistor array where the emitter is one nwell resistor (N doping), the base is your substrate (P doping) and the collector your other resistor (N doping).  (note: which resistor is the collector and emitter are interchangeable in this discussion)  Your Nwells are spaced closely, probably at minimum pitches for the process which means, considering lateral diffusion creeping, the nwells could be much closer together.

You did a good thing by placing P+ guardrings between the resistors, but I note that they are contacted by only 1 via or contact and very thin metal for a few squares.  This is possibly a resistive guardring which can dramatically reduce its effectiveness, or in this case make snapback worse because we now have a resistive load on the base of our NPN.  

Comment on NPN snapback:  (True of any parasitic NPN device)
If the Base is floating, snapback is very difficult to induce because there is no place for base current to flow, no I_B, no beta gain; if the base is hard shorted to the emitter, snapback is also very difficult to induce because it take a huge amount of base current to create a V_BE > 0.7V in order to turn on the NPN; in your case you have a definite current path for base current, which is resistively connected to ground and that ground is isolated from both the emitter and collector meaning that generating a V_BE  to turn on the NPN is very possible, at even small base currents.

Back to the discussion:  So your lateral npn devices in your resistor array are quite prone to snapping-back, despite the P+ guardrings, or possibly because of the P+ guardrings. hard to say.

Whats worse, if the NPN does snapback, the energy and voltages that will be passed will pass directly to the gate oxide of the complementary diff pair pin,  worse still is that this energy is isolated again by nwell resistor meaning that a stress on pin1 that induces snapback on the nwell array will then expose pin2's oxide directly to the ESD event...worse still the esd energies on pin2 oxide are now isolated from pin2's ESD protection structures by the nwell resistor that is snapping-back, whereas pin1, is still being protected local to some degree by his ESD structures.

So why would it fail in one polarity, but not the opposite polarity with pins reversed, which technically would use the exact same current paths?

My suspicion is that it depends on the nwell resistor array and how it is laid, both resistors to each other and  with respect to ground.  Remember that during an ESD event, the ground domain is also charged up to a point depending on the ESD current paths.  Also, Lateral NPN snapback is very layout dependent and it is possible that when we reverse the polarities but use the same current path the exact triggering mechanism of the snapback is not longer the same.  

It is also possible that the physical location of snapback in the array, based on layout, places pin2s oxide closer to the esd event, while pin1 ones oxide is further isolated because the ESD energies are dividing down between what passes to pin 2 and whatever resistance is left in pin1 current path.  This could easily explain the unidirectional failure.


Essentially though, the mere solution being that you replaced nwell resistors with poly would indicate that it is indeed your lateral NPN snapping back across the two pins, and then the isolated energies destroying the exposed oxide of the complementary pin.  I bet also that your poly resistors are even a little smaller in terms of resistance...which would baffle most people because you expect higher resistance to help.  In this case, the resistance is likely being ignored as the ESD energies find their own (parasitic) paths.  (Which is what they are very good at).

Anyway, thats enough talk from me... This is an interesting problem, but I believe it is reasonably explainable.

I hope this helps,
Stephen