Hi all, I am trying to design a gate driver of external switching mosfet of a SMPS.  The whole circuit is actually a boost DC-DC, but working in a open loop condition, no feedback from output.  If given a 50% duty cycle, a 2*Vin is expected at the output.  No feedback.

First question is I want to know how to define  the capacity of the driver of external mosfet, to get a reasonable delay time, aiming for small error between duty cycle of gate control signals and reciprocal of boost ratio,  and a reasonable efficiency.  I don't get clear requirement of them. What are the general procedure and aspects which should be considered in this design?  And how to estimate the power dissipation of external mosfet in switching mode with finite gate driver and parasitic drain capacitor?

Second question is how to describe the external mosfet?  Now i just get the spec of external mosfet, but there are some parameters confusing me, Qg, Qgs, Qgd--(gate charge), Cin, Cout, Creverse--(tested @ 1Mhz). I've seen a model file of a certain kind of mosfet supplied by producer. NMOS, PMOS (used as Cgd) and cap (between g and s )are used to construct the model. But after simulation, i found that just Cin is similiar to the value of it in spec. So i am confused.  Which parameters in spec of external mosfet are critical for the whole circuit that must be accordant in model?  What's the normal way to describe this mosfet in simulation?  And if i want to describe it in Verilog A, which parameters should be included and how to write it?

Third question is how to model the inductor with variable resistor?  I found in the spec of inductor that there is a variable resistor series with inductor,  with a value a*sqrt(f). f is frequency of I in inductor.   In my opinion, this resistor just affect in AC signal, so the power on it is just related with the AC part of I in inductor.  Is there any way to write it in language in Verilog A or describe it directly in schematic?

Great Thanks for your help, any response is welcomed