I want to improve the VerilogA file that I use to write data to a text file.  The current version works but does not allow me to change the file name during execution of the program.  I tried using the the STRCAT function to concatenate a two strings but that does not work.

Here is what I currently have that works.

`include "disciplines.vams"
`include "constants.vams"

module sink_IQ(vi,vq);
   electrical vi,vq;
   parameter string file_name = "dat1_out.tbl";
   parameter real T_step = 1e-9;
   integer file_ptr, hdrPrinted;

   analog begin
       @( initial_step ) begin
          file_ptr=$fopen(file_name);
       end

       @(timer(0,T_step)) begin
         $fwrite(file_ptr, "%e %e %e\n", $abstime, V(vi), V(vq));
       end

       @ (final_step) begin
         $fclose(file_ptr);
       end
   end
endmodule

I would like to add a line like
    file_name = strcat(file_name,suffix);
within the code to allow me to change the file name. Is there another way to do this?

Thanks,
Makelo

The concatenation operator addresses your need.

Example:

`include "constants.h"
`include "discipline.h"

module add_str( in1, in2 );

input in1, in2;
electrical in1;
electrical in2 ;

parameter string filename = "foo" ;
parameter string file_ext = ".bar" ;
string concatenated ;

string var1 ;
string var2 ;
string concat_var ;

analog
       begin
          V(in1,in2) <+ I(in1,in2) ;
          concatenated = { filename, file_ext};        
          $strobe("concat from params:%s ", concatenated ) ;

          var1 = "car" ;
          var2 = ".shar" ;
          concat_var = {var1, var2} ;
          $strobe("concat from vars:%s ", concat_var ) ;
       end
endmodule