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Croaker Senior Member Offline Posts: 235	join strings May 15^th, 2007, 11:13am How do you join strings with Verilog-A? str1 = "a"; str2 = "b"; I want to have str3 = "ab".
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Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA	Re: join strings Reply #1 - May 16^th, 2007, 7:29am You can't do this presently, not least because Verilog-A doesn't really have strings in the first place. Verilog-AMS has "string literals" from digital Verilog, which can be stored in "reg" variables (registers) of 8 bits per character, and these registers act as though they are integers. Verilog-A specifically excludes reg.
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DReynolds Junior Member Offline Posts: 15 Scarborough ME	Re: join strings Reply #2 - May 17^th, 2007, 10:19am Croaker, as mentioned, the language really doesn't deal with string manipulation: I have found it easier to do my string manipulations in another language (python, perl, skill) and then just dump it into a file that I stitch into the veriloga. David
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chetan

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Re: join strings
Reply #3 - May 30^th, 2007, 11:55am

Verilog-A does allow string variables ( plane variables - apart from the registers ) as well as parameters. The string parameters are treated differently than variables. For joining the strings the concatenation operator works.

I've already anwsered a similar post titled ' string variables in Verilog-A'. See if this link works: http://www.designers-guide.org/Forum/YaBB.pl?num=1177696583

That post gives an example.

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Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA	Re: join strings Reply #4 - May 31^st, 2007, 3:47am chetan wrote on May 30^th, 2007, 11:55am: Verilog-A does allow string variables No, it doesn't -- it's not part of LRM 2.2. The V-AMS committee is working to include them in LRM 2.3, based on the definition in SystemVerilog. Perhaps your simulator has an extension that allows string variables?
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