RobG
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I can't think of any good reason to have a cap from Vdd to your output, but I don't think it is causing the overshoot.
I think it is just the response time of the opamp... Upon startup, the op-amp output will be forced to the bottom rail by the startup circuit. That will pull your BG output to the top rail. The opamp's bandwidth suggests response times on the order of uS, and that is what you are seeing.
In addition, your particular compenstation scheme will cause overshoot in response to Vdd changes. This isn't obvious, but consider this: Your opamp compensation is referred to the bottom rail. If the top rail has a high-speed step, the gate-source voltage of your PMOS mirrors will change by the same amount (the compensation prevents the opamp from changing quickly), and you will see a big bump on VBG. You would have to redesign the opamp to get around this (e.g. a folded cascode with compenstation from output to positive rail). If you do this I think you will have better startup characteristics.
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