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capbank vco verilog-a modeling (Read 71 times)

memnon New Member Offline Posts: 1	capbank vco verilog-a modeling May 10^th, 2007, 10:54pm I need to verilog-a modeling of 6bit capbank vco. please, help me.
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Geoffrey_Coram

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Posts: 1998
Massachusetts, USA

Re: capbank vco verilog-a modeling
Reply #1 - May 15^th, 2007, 4:06am

Ways to make a Verilog-A model:
1) Read a book (Designer's Guide to Verilog-AMS)
2) Read the LRM
3) Find some examples from the V-AMS link in the upper-right of this forum

Ways to annoy people on this forum:
1) Ask us to do your homework for you

Please come back when you've at least tried to do this yourself and have a specific question or problem.

If at first you do succeed, STOP, raise your standards, and stop wasting your time.

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Eugene

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Posts: 262

Re: capbank vco verilog-a modeling
Reply #2 - May 29^th, 2007, 8:17am

The original quesiton has a practcial problem too. Even if someone had a ready-to-use model, by posting it they would most likely violate an agreement they signed with their employer regarding intelletual property. Most employers are very sensitive about anything an employee developed on company time. They consider it intellectual property. When they do allow it to be published, they thoroughly review it and want it published in a journal or conference proceedings and they want proper recognition.

However, if you have a piece of code which you want critiqued, we can probably help you without getting into trouble with our employers, as long as we do so on our own time.

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