I don't know where my initial post is! but ...here it is!

hi all!
I would like to design a cascode configuration and my target are:
- gain ≥ 20
- Vout DC ≈ 1.8 volt

I calculated some values on paper and I simulated my circuit but the
results are completely different!
my circuit is here: http://www.thebags.it--out-of-date/listing/uni/cascode.png

if I want Vout = 1.8V
Rd*Id = 1.5V; Rd = 600ohm so Id = 2.5mA

if I want Av = gm2 * (Rd//r02) = 20 I have to choose Vov = 0.10V and
so Vgs = 668mV

if I want Id = 2.5mA and Vov = 0.10 W has to be W=1080u

...I set these values in cadence but the risult is completely
different! Can you try to explain me why?
any help is appreciated

thank you (and sorry for my english..)

Hi Matteo,

I meant the bottom transistor. The VDS is only 0.047 V. And VGS is 0.668 mV. So the bottom transistor is either in weak inversion, or triode region depending on your VT.

The gain would be 1 from gate to drain of the bottom transistor only if both transistors have the same gm. The cascode transistor has the effect of increasing the output resistance. If you read "design of analof CMOS integrated circuits" by rasavi, I think it shows somewhere how to calculate the gain. It should be something like:

Av = gm1 . [( r01+r02 + (gm1 +gm2).r01r02)//RD]

Anyway if you want more gain you should definately increase the gate bias voltage of your cascode transistor.

Berberephone,
    Please do not change the topic of a thread. It is much better to simply start a new thread. Please read and follow the Forum Guidelines (http://www.designers-guide.org/Forum/guidelines.html).

-Ken

Hi,
If you have the S parameters matrix, the diagonal parameters(S11,S22,S33) are the reflection coefficient at ports 1,2,3 respectively. With these data you can find the input impedance of each port(which is directly related with reflection coefficient). When you have the input impedance you can design a matching network using discrete components or transmission lines(ustrip or coplanar usually). Take a look at:
http://www.sss-mag.com/pdf/AN154.pdf

Hi,
I didn't use ADS usually also, but you don't need it to calculate a matching network with transmission lines once you have the impedances. Here's a link for the best tool to design matching networks with transmission lines: http://ieee.engsoc.org/v2.0/resources/smithchart/smithchart.pdf.
As a teacher tolds me years ago:"You won't be a Microwave/RF Engineer unless you know how to use this piece of paper"
Good Luck,

Hi,
Sorry, I assumed that you want a matching with transmission lines. Try this website:http://home.sandiego.edu/~ekim/e194rfs01/jwmatcher/matcher2.html, I've found this web a couple of years ago when I was designing a PCB but finally I didn't use it so I can't guarantee the results accuracy, maybe it could help you. It's pretty easy to use and give you several options to play with,
Good luck,
PS: don't call me professor please, i'm just a grad student.

ok thank you, please I will ask you for a solution has a thing: I have a problem with regard to the polarization of my transistors for dual mixer gate (OL in linear zone and RF in zone saturee) for that I use the mirrors of current to make polarize them but I do not arrive has to operate them effective menieres of such kind to polarize transistor LO by a signal close to his Vth, I signal DIDAC that I work with the food 1.2V and in a technologie065nm and with ELDORF. stp if you can give me exactly dimensions of different the values from components (W, L and resistances) has fine to operate my transistors in their zones of operation. mixer thus must work as follows: - transistor OL in top works as switch (linear) - transitor RF in bottom works in saturation I will not forget you your assistance DIDAC and I excuse myself for the disturbance.

I see sending in file attaches the structure of my dual mixer gate

I waits has you answer and your remarks!!