Hi, folks

I try to design LDO with 35uVrms output noise at 100~100KHz, using 0.6um standard digital CMOS process.
The feedback gain of LDO is 2.5. So in my calculation, input referred noise of LDO should be less than 14uVrms to reach the spec.
Is it possible to design?
if I increase quiescent current, I can reach at the spec easily. But in my spec, my quiescent current is just 50uA.
And also, I try to increase input device size of error amplifier, but this doen not work.
Is it possible to implement LDO with standard CMOS process? or should I change process such as bi-CMOS?
Could you please give me any info to implement low noise LDO?

Best regards,

Won

Thanks Faisal.
I assumed that I can filtered out noise from bandgap.
I'd like to use unity gain feedback LDO.
But I can not use unity gain feedback LDO configuration due to spec.
So dominant noise contributor is error amplifier.
Using large input device of error amplifier can help to reduce noise, but I can not meet the spec.
is any method to reduce noise?

Best regards,

50u is not so low for a LDO design. You might want to decrease the current consumption in other areas of your design to make more current available in the error amplifier. Possible places to reduce power consumption could be to increase the resistors value in the feedback network. If you are using buffer to drive the pass transistor, make sure that you dont spend more than necessary power there.