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guerreiro New Member Offline Posts: 5	How 2 lower the PSRR in a delta Vbe current source May 24^th, 2007, 2:15pm Hello. I'm trying to make a ΔVbe currente source and a need to lower the PSRR. I'm using a topology that is in the attachment. Is there anyone that could explain me how to do it? Thanks.
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sheldon

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Re: How 2 lower the PSRR in a delta Vbe current so
Reply #1 - May 24^th, 2007, 8:42pm

Guerreiro,

It looks like you already have a good start. A couple of questions/
things to consider:
1) What is your supply voltage?
--> Is there enough headroom to add more cascoding?
2) Where are the bulk nodes of M4, M5, M7, M8, M10 tied to?
If you tie the bulk nodes of M7, M8, and M10 to their sources
that should increase PSRR
If you have access to a triple-well process, then you could
isolate the p-well for M4 and M5 and short the substrate
and source.
3) You don't mention where you are losing PSRR, if the issue
is not the core, then it may be in the output stage.
You could replace the current cascode at the output with a
gain boosted source, however, you will need to be careful
with biasing.

Best Regards,

Sheldon

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guerreiro

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Re: How 2 lower the PSRR in a delta Vbe current so
Reply #2 - May 25^th, 2007, 9:04am

Thank you sheldon,

I think that it could be a bit difficult to add cascodes because my VDD is 3.3V and my Vss is 0V, but I do not know for sure if that's a problem.

The technology I'm using (0.35μ) doesn't permit a triple-well process so, I have one substrate for the N transistors and one n-well for the P transistors. In that case I have the p-substrate connected to the ground and the bulk of the P transistors connected to VDD.

What I'm measuring is ΔIo/ΔVDD, that is, the effect in the output current of some variation on the DC voltage source. To do that I'm using an AC analysis performed in Cadence Software. I think that's the way to do it, but I'm not sure.

I has told to get a good PSRR, but I'm getting a curve that crosses 0.2μA/V at 1.2MHz.
I think that's not very good because I have a digital circuit to feed, that is going to operate at least at 4MHz and I will deliver 1μA per current source.
The whole circuit will have 8 current mirrors, but that I think is not a problem.

I tried to put 2 caps between the source and gate of the M3 and M7 transistors, but it only made that crossing point to increase a little in frequency.

Could you please show me a way to do the gain boosted source. My problem is how to bias that kind of topology, because I'll have to use an amplifier, right? If that's true, I'll need a current source to feed the amplifier and I don't know how to do it.
You see, what I have to do is to create one current source...

Once again, thank you for your attention.

Guerreiro

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RobG

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Bozeman, MT

Re: How 2 lower the PSRR in a delta Vbe current so
Reply #3 - May 25^th, 2007, 10:22am

guerreiro wrote on May 25^th, 2007, 9:04am:

I has told to get a good PSRR, but I'm getting a curve that crosses 0.2μA/V at 1.2MHz.
I think that's not very good because I have a digital circuit to feed, that is going to operate at least at 4MHz and I will deliver 1μA per current source.
The whole circuit will have 8 current mirrors, but that I think is not a problem.

I tried to put 2 caps between the source and gate of the M3 and M7 transistors, but it only made that crossing point to increase a little in frequency.

Ahh.... you are after AC PSR. Further cascoding, etc is probably only going to boost the DC PSR.

A large cap across the gate/source of M9 should filter any noise from the delta-Vbe source itself. If you are still getting AC noise, then it must be coming from the cascode device M9. About all you can do about that is make it small to minimize parasitic capacitance. You can also add capacitance across the gate-source of whatever device you are biasing.

AC analysis is good for a rough idea, but also check transient response if AC rejection is critical. AC currents in nonlinear devices cause DC shifts in the current. These shifts are generally proportional to the square of the AC ripple.

rg

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RobertZ

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San Diego, CA

Re: How 2 lower the PSRR in a delta Vbe current so
Reply #4 - May 25^th, 2007, 11:59am

Why can shorting source an bulk improve PSR?

[quote author=sheldon link=1180041359/0#1 date=1180064525]Guerreiro,

2) Where are the bulk nodes of M4, M5, M7, M8, M10 tied to?
� � If you tie the bulk nodes of M7, M8, and M10 to their sources
� � that should increase PSRR
� � If you have access to a triple-well process, then you could
� � isolate the p-well for M4 and M5 and short the substrate
� � and source.]

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Thanks,
Robert

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RobertZ Community Member Offline the art of analog Posts: 55 San Diego, CA	Re: How 2 lower the PSRR in a delta Vbe current so Reply #5 - May 25^th, 2007, 12:01pm bias PMOS such that they have small Vdsat and large Vds across them. Will this help?
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guerreiro

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Re: How 2 lower the PSRR in a delta Vbe current so
Reply #6 - May 25^th, 2007, 12:22pm

Thanks all!

I will try to lower the size of the upper Ms to lower the parasitic and to lower Vdsat..
Still I don't want the transistors to enter the triode region, and I think that M7 will enter triode...
The bias current is constant and equals 1μA.

I think it will improve in something.

I'm going to try...

Guerreiro

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RobertZ Community Member Offline the art of analog Posts: 55 San Diego, CA	Re: How 2 lower the PSRR in a delta Vbe current so Reply #7 - May 25^th, 2007, 2:37pm If headroom is an issue for you, maybe using low swing cascode will help you. But be careful with cascode bias generation, you may end up with lots of loop.
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imd1 Junior Member Offline Posts: 27	Re: How 2 lower the PSRR in a delta Vbe current so Reply #8 - May 26^th, 2007, 2:24am If you are using AMS C35 0.35um technology you'll have to use LV cascodes as suggested above otherwise you won't have headroom over PVT corners (I think..., if automotive range at least). BTW, isn't there a start-up circuit somewhere ?
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