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joel

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VCO Jitter Question
May 31^st, 2007, 1:59pm

Hi All,
I'm trying to learn about VCOs, and would like to get a sense of design trade-offs. Could someone tell me...

Does increasing the number of delay-cells in the VCO chain increase or decreas the jitter, assuming the frequency is kept constant?

How much improvement should I expect by replacing a single-ended delay-cell with a differential cell?

Does hspice circuit-simulation give any indication of actual jitter in a stable environment (e.g. not a PSRR simulation)?

And finally, what books & articles should I read to educate myself sufficiently to design CMOS VCOs for PLLs in the 500MHz-3GHz range?

Thanks in advance for your attention,
~joel

ps... after some web surfing, I think I've learned that LC oscillators are the circuit of choice for GHz range PLLs. Maybe someone can help me with a few words of explanation regarding the advantages of LCoscs over ring-oscs? Thanks again, /jd

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ywguo

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Shanghai, PRC

Re: VCO Jitter Question
Reply #1 - May 31^st, 2007, 11:31pm

Hi, Joel,

That is a very complex topic. I am afraid that I cannot explain it in a short post. You'd better search ieeexplore to find some papers. Some theses on univerity websites are very good, too.

Generally LC osc has better phase noise and jitter than ring osc. However, depending on the applications, ring osc is good enough in some gigabit circuits, too.

BG
Yawei

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joel

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Re: VCO Jitter Question
Reply #2 - Jun 2^nd, 2007, 11:51am

Thank you for the suggestions! I've been trying to do my homework, working through 3 phaselock books. Unfortunately they offer more analytical than practical knowledge. Perhaps the answer will be in the VCO book I just ordered from this site, but please let my pose my immediate concern.

I am looking at a chip with 2 PLL designs in it. Both use ring-osc VCOs, but one is 3-stage single and the other is 4-stage differential. Both receive the control voltage through what I believe is a standard cascoded VtoI into their top (P) sides. Boss wants their performance to be improved for the next spin. So I wonder if going to a 2-stage differential VCO would be better, or something else?

You'd think this would be an ideal chip to answer my previous question. But here's the weird thing: The oscilloscope shows them performing almost identically with 400pS P-P, ~50pS RMS jitter at 600MHz f(VCO). Even when I change the charge-pump current and VCO gain, which is programmable.

So I wonder if I'm really just measuring my test setup, or the power supply. Maybe the deadbands dominate the jitter/skew behavior. Maybe I should move this discussion to the Measurement topic area!

Thanks in advance for any insight you can offer me. Cheers!

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Berti

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Re: VCO Jitter Question
Reply #3 - Jun 4^th, 2007, 12:12am

Hi Joel,

The jitter of a ring oscillator is independent of the number of stages. You measurement therefore just confirms the theory.
Nevertheless, if no quadrature outputs are required, ring oscillator with 2 or 3 stages consume less power for the same
jitter than oscillator with 4 stages or more.
In my experience, jitter is often dominated by flicker noise (also at higher frequencies)
when using advanced technologies. Increasing the area of the devices or not using the current source for frequency tuning
therefore often helps to reduce the phase noise (jitter).

Replacing single-ended with differential delay stages only improves performance when you jitter is dominated by supply noise.
However, this is a complex subject and depends on the enviroment on your chip.

I think it is difficult to predict jitter with a noise simulation using a stable operating point since a delay stage is not necesseraly
most sensitive to jitter only at the switching moment.

Cheers,

Thomas

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