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how to model the nonidealities of opamp?verilog-A (Read 2317 times)
senyou78
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germany
how to model the nonidealities of opamp?verilog-A
Jun 10th, 2007, 11:31am
 
hi,
I do some research in delta-sigma modulator,I m using verilog-A and cadence.I want to model the nonidealities of a differential opamp that I am using in my circuit,I donīt know how to model that in verilog-A !using the macromodel of diff-opamp(like the the input/output resistance of the opamp.
is their any good coding which help me to analyse the non-idealities of the opamp?
thanks
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boe
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Re: how to model the nonidealities of opamp?verilo
Reply #1 - Jun 11th, 2007, 5:23am
 
hchanda posted a nice model (OK, it's single-ended, so you'll have to add the differential output): http://www.designers-guide.org/Forum/YaBB.pl?num=1165362179/5#5.
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senyou78
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Re: how to model the nonidealities of opamp?verilo
Reply #2 - Jun 11th, 2007, 12:06pm
 
thanks
I ll try it Wink
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