I want to write a digital buffer with inertial delay in Verilog-AMS. The digital output is the same as input with delay time "t_delay" except the input pulse time "t_inertial" smaller than half of "t_delay".

For example, the buffer has tow parameters, t_delay and t_inertial = [0:t_delay]. If the digital input pulse time (no matter up/down) is bigger than t_inertial, the output is the input with delay t_delay. Otherwise, the output is unchanged.

Does Verilog-AMS have the similar system function to realize it?

Thanks a lot,