Peter,

I have been working on a PLL design with a similar architecture and have learned quite a bit about it through simulations, and have some observations I can share with you.

Concerning the ring oscillator startup: this isn't an isse with this PLL architecture.  For instance, say the VCO control voltage is referenced to VDD.  Also, assume the amplifier in the replica bias generator is a PMOS diff-pair topology.  So, if the loop starts out such that the control voltage is zero (i.e. it is at VDD) then the VCO output is static.  Therefore the feedback to the PFD is static.  Assuming the reference signal is applied to the input, the PFD will produce large phase-error pulses.  The charge pump will then start charging the loop filter cap toward ground effectively increasing the control voltage to the bias generator.  Eventually, the VCO will begin oscillating and the loop should settle for propperly designed system parameters that control the loop dynamics.  However, startup problems can exist for the bias generator amplifier itself if it is self biased, but there are well established techniques in the literature for this problem.

So, the ring oscillator in this case will be at zero frequency for zero control voltage, and will have an upper frequency limit (at full control voltage) that varies with the number of delay stages and device sizes, as well as PVT variations.  One thing to watch out for is to make sure the upper speed limit of the feedback divider exceeds the upper limit of the oscillator.  Otherwise, if the control voltage is near ground when the loop starts up, I think it could be possible for the VCO to start out at a really high frequency which could cause the loop to "latch up" if the divider cannot keep up with the VCO.  Of course, peaking in the system transfer function can also get the loop into this state if this condition (or other preventative means) is not met.

Good luck!