Hi,

in the past, we were verifying connectivity of a schematic (in Cadence Virtuoso) by netlisting it with vhdlNet,
filling out the modules with models, and simulating that in the digital realm.
We would map analog ports to a user-defined type in pure VHDL (a record type made from an integer value
and an abstract portion), and in order to get the port types correct, we set the
vhdlDataType property of each port. This worked pretty well, a port would look like

   vout : out our_vhdl_type;

Now, we are moving to VHDL-AMS though, and I can't find a way to get

   terminal vout : electrical;

out of vhdlNet.

The only way I see right now is to post-process the generated files, but if I can avoid this...

Any hints welcome.

Thanks
 Colin

As you have found out the hard way, the vhdltool box does not support VHDLAMS or the analog extensions to vhdl.
There are already PCRs asking for this support from others.
You will have to post-process the vhdl tool box netlist to add the analog ports/types as you are already doing.

thanks
Rick