Prathap
New Member
Offline
Posts: 7
India
|
Hi, I just wanted to know whether usage of already available simulations results is possible in Verilog A. Like for instance giving the available results as an input to one of the input ports in a Verilog A module.
To be more tool specific, one knows that the simulation results get stored as a 'psf' file in a Cadence environment. So is there any possibilty to include the psf data as a file to make it the source of a input port.
Thanks, Prathap.
|