How to add white noise to a model
? i want to model the nonidealities of the first order (switched capacitor)delta-sigma modulator,I realized the circuit in verilog-A every module is written in verilog-A except the switch which is realized with transistor level(because I had lot of troubles with switch model).I allready modeled the non-ideality of the opamp(dc gain,slew rate,etc...),and now I want to implement the oder nonidealities concerning capacitor noise,thermal noise,switch......
is there any materials which could help me to anderstand and realize the non-idealities of D-S modulator?
thanks