Hi Geoffrey and All,
The genvars are giving me some hard times these days. I was mainly confused because it appears like genvars are not supported the same way in VerilogD and VerilogAMS (
http://www.verilog.org/mantis/view.php?id=812).
My current understanding with genvars in Verilog-AMS is they must be used as index of for loops in the following couple of cases:
1. Access to the analog signals in busses from within analog processes.
2. When analog operators (like transition) are invoked in a for loop
However, you have stated above:
Quote:If you have a contribution V() <+ inside a for loop, then the condition is not allowed to depend on variables, only constants and parameters.
Is the above statement part of the VAMS LRM ?
Would you expect the following loop to be needing i as genvar (although this is unlikely to be a real world example) ?
analog begin
for(i=0; i<3; i=i+1)
V(myAnalogNode) <+ i;
end
Thank you very much in advance for enlightening me.
Cheers,
Riad.