Hey all,
I'm currently learning verilog. I'm trying to make a test bench to
simulate a binary-to-7-segment decoder. I've broken the circuitry up
into individual logic circuits for each segment (a-g); so I have 7
logic circuits total.
I want to see how each of these individual logic circuit would respond
to a series of identical waveforms. So instead of making separate
verilog files for each of the logic circuits, I decided to dump them
all in a test bench. But in doing so, I've made some mistakes and cant
figure out what they are.
I'm not concerned (ATM) with whether the logic circuits are functionally correct, right
now I want to get the test bench up and running. Please help.
Thanks :)
Code:module testBench;
wire [6:0] w1;
wire w2,w3,w4,w5;
binaryToASeg a(w1[6],w2,w3,w4,w5);
binaryToBSeg b(w1[5],w2,w3,w4,w5);
binaryToCSeg c(w1[4],w2,w3,w4,w5);
binaryToDSeg d(w1[3],w2,w3,w4,w5);
binaryToESeg e(w1[3],w2,w3,w4,w5);
binaryToFSeg f(w1[1],w2,w3,w4,w5);
binaryToGSeg g(w1[0],w2,w3,w4,w5);
Func_gen_and_disp disp(w2,w3,w4,w5,w1);
endmodule
module binaryToASeg //Segment A
(input b3, b2, b1, b0,
output aSeg);
and g4(aSeg,~bo,~b3,b2);
endmodule
module binaryToBSeg //Segment B
(input b3,b2,b1,b0,
output bSeg);
and g1(p1,~b1,b0,~b3);
and g2(p2,b1,~b0,~b3,b2);
or g3(bSeg,p1,p2);
endmodule
module BinaryToCSeg //Segment C
(input b3, b2, b1, b0,
output cSeg);
and g1(p1,~b3,~b2,~b1,b0);
and g2(p2,~b3,~b2,b1,~b0);
or g3(cSeg, p1,p2);
endmodule
module BinaryToDSeg //Segment D
(input b3, b2, b1, b0,
output dSeg);
and g1(p1,~b3,b2,~b1,~b0);
and g2(p2,b3,~b2,~b1,b0);
and g3(p3,~b3,b2,b1,b0);
or g4(dSeg,p1,p2,p3);
endmodule
module BinaryToESeg //Segment E
(input b3, b2, b1, b0,
output eSeg);
and g1(p1,~b3,b1,b0);
and g2(p2,~b3,b2,~b1);
and g3(p3,b3,~b2,~b1,b0);
or g4(eSeg,p1,p2,p3);
endmodule
module BinaryToFSeg //Segment F
(input b3, b2, b1, b0,
output fSeg);
and g1(p1,b1,~b3,~b2);
and g2(p2,b1,b0,~b3);
or g3(fSeg,p1,p2);
endmodule
module BinaryToGSeg //Segment G
(input b3, b2, b1, b0,
output gSeg);
and g1(p1,~b3,~b2,~b1,~b0);
and g2(p2,~b3,b2,b1,b0);
or g3(gSeg,p1,p2);
endmodule
module Func_gen_and_disp //here is where I make the waveform and
//print the results.
(output reg b3,b2,b1,b0,
input [6:0] Seg);
initial
begin
$monitor
($time,,,"b3 = %b b2 = %b b1 = %b b0 = %b, aSeg = %b,
bSeg = %b, cSeg = %b, dSeg = %b, eSeg = %b, fSeg = %b, gSeg = %b,",
b3,b2,b1,b0,
Seg[6],Seg[5],Seg[4],Seg[3],Seg[2],Seg[1],Seg[0]);
#10 b3 = 0; b2 = 0; b1 = 0; b0 = 0;
#10 b3 = 0; b2 = 0; b1 = 0; b0 = 1;
#10 b3 = 0; b2 = 0; b1 = 1; b0 = 0;
#10 b3 = 0; b2 = 0; b1 = 1; b0 = 1;
#10 b3 = 0; b2 = 1; b1 = 0; b0 = 0;
#10 b3 = 0; b2 = 1; b1 = 0; b0 = 1;
#10 b3 = 0; b2 = 1; b1 = 1; b0 = 0;
#10 b3 = 0; b2 = 1; b1 = 1; b0 = 1;
#10 b3 = 1; b2 = 0; b1 = 0; b0 = 0;
#10 b3 = 1; b2 = 0; b1 = 0; b0 = 1;
#10 $finish;
end
endmodule
P.S. Remember that I'm new to the world of verilog, so if you have any suggestions on how to do this in a more efficient way, please do tell.