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Help with test bench (Read 10146 times)

Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA	Re: Help with test bench Reply #15 - Jul 09^th, 2007, 6:30am In several of the segments, you have intermediate results, eg binaryToBSeg has p1 and p2. Do you need to provide some sort of declaration for them?
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boe

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Re: Help with test bench
Reply #16 - Jul 9^th, 2007, 7:36am

Geoffrey_Coram wrote on Jul 9^th, 2007, 6:30am:

In several of the segments, you have intermediate results, eg binaryToBSeg has p1 and p2. Do you need to provide some sort of declaration for them?

Cadence tools (V-XL and NCSim) do not require this. All variables that have not been specified are implicitly declared as scalar wires.
I haven't checked the Verilog standard, though...

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