Hey guys,
I figured it out (thanks to my boss!)

You don't have to 'generate' schematic out of layout. Do the usual way. just add lvsIgnore labels when you want a certain element to be discounted in layout.
In my case, i need the actual  plate cap between the metal layers. So, I put analogLib capacitors in schematic and ignore them in LVS.
Once, LVS is clean, extract the netlist and I get the plate cap  8-)