In plain verilog,

always@(b1 or b2 or b3)

will detect changes in b1, b2 or b3.

If I write

logic b1, b2, b3;

analog begin
@(b1 or b2 or b3) blah;
end

The elaborator complains that the left operand of type integer is not supported for operator "Event OR".
Writing:

analog begin
@(b1 || b2 || b3) blah;
end

works, but it not the same.

How can I get event-OR to work within an analog block?

Thanks,

Seb

It turns out that digital lines are converted to integers within an analogue block, which gives raise to the problem I commented.

The bug in verilogAMS has been solved newer versions of IUS.