In 1997 Dec. JSSCC, Aaron Buckwald raised cascaded folding concept in high speed ADC to reduce No. comparators.

The approach there is to first folding x3 and cascade another folding x3 after it.

I do not quite follow his paper. Since folding will induce large distortion and only zero crossing is used, further folding does not have a good reference voltage. How we give 2nd stage folding x3 a good reference?