Hi,

I have recently started to develop AMS environment(Cadence Virtuoso AMS) at chip level.
The testbench components are System Verilog and the design is mixed verilog  + vhdl.

While running verilog -irun ...command, i see some issues in ncelab. The error is something like -
Hierarical component lookup failure testbench.top.......cfash0.ftop.IFLH

FYI, the same pattern runs fine when run without ams options i.e without giving -propspath option in the verilog run command.
Also the testbench is SV, top, cfash0 is verilog code, ftop is a vhdl code whereas IFLH is verilog.

The cflash0, ftop, IFLH are all digital blocks.

Any clues why do i see this issue?

Thanks,
Leena