savithru
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hi
I am using the verilogA model for the frequency divider given in the pdf "Hidden State in SpectreRF" by Ken Kundert, Designer’s Guide Consulting, Inc.
You have used the following
module divideByN(pout, nout, pin, nin);
Here you defune the module by the name divideByN with pout, nout, pin, nin as ports.
But I could not undestand what are these Pout and Pin ports.
kindly reply.
Regars SavithRu
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