Designer’s Guide Community

Pages: 1

65 nm layout issues, WELL proximity etc.. Help me (Read 2032 times)

silicon_holmes New Member Offline Let there be light ... Posts: 6 Bangalore	65 nm layout issues, WELL proximity etc.. Help me Jul 19^th, 2007, 7:47am Hi all, Will anybody please help me with "Well proximity error" ? What exactly is this? what is it's impact on device performance? how can it be taken care in layouts? can anybody give me an idea of similar issues in 90-65nm processes? Thanks in advance,
Back to top	IP Logged

didac

Senior Member

Offline

There's a million
ways to see the
things in life

Posts: 247
manresa,spain

Re: 65 nm layout issues, WELL proximity etc.. Help
Reply #1 - Jul 19^th, 2007, 8:47am

Hi babya,
Months ago doing a little google search I found this interesting paper:http://www.solidodesign.com/publications/1_drennan_cicc06_v3f.pdf, it explains very clear the new issues due to sub 100nm technologies. As it is stated well proximity causes differences on threshold voltage and creates also asymmetric behaviour between S/D.
Hope it helps,

IP Logged

Pages: 1

‹ Previous topic | Next topic ›