When I simulate my oscillator by pnoise analysis (noiseType=sources) and try to investigate the output noise current by a probe as shown in the following Fig. I find there is a spike at the oscillating frequency in the output noise current. What's the reason for that spike? Is there any physical meaning or just due to some effects of the simulator.

As to the oscillator shown, bias current is from an ideal current source; the behavior of transistors are describled by Verilog-A without capacitive and noise effect; and I use a VCCS to model the thermal noise current with PSD 4kTR, which is the only source of noise.

In my understanding  the output noise in my case is cyclostationary,  and it is also a white noise with a flat PSD.

-JC

sheldon,

Thanks for your reply.
1. My tolerance settings are: errpreset =  "conservative" ; iabstol = "1e-13"; vabstol = "1e-7"; reltol = "1e-5". These settings are recommended by some people,  but comparing with the result value it seems they are not enough.
2.The center of spike resides at the oscillating frequency. And the shape shows a little similarity with phase noise plot.
Since I use the ideal components, which means they don't generate noise e.g. for resistor with option "isnoisy=no", and the FETs use behavior model wrote by verilog-a without noise and capacitive effects, the only noise source is implemented by a vccs controled by a noisy resistor as shown in the Fig.
I wander it maybe caused by the positive feedback of OSC and the V->I conversion of FETs, which converts the noisy voltage near the oscillation frequency to noisy current with a gain large than 1. So the amplitude of that noise current PSD is large than that of the only noisy source. Is it correct?

-JC

Ken Kundert wrote on Jul 26^th, 2007, 3:13pm:

Thanks for reply.
Yes, I think the spike should be the phase noise. And  I still have some doubts about the procedure of the conversion from noise current source with flat PSD at tail to output noise current with that shap.

-JC