Check the paper archives at http://www.bmas-conf.org for papers using VHDL-AMS, and see where the authors are working.  Mostly European, I think.

Hi Jess,
I don't know if this is the reason but in my experience here in Spain VHDL is the language that it's used in the compulsory subjects(in free elective subjects Verilog and SystemC are introduced and used) because the labs are done with FPGA's(and when I did these subject I think the vendor's software only supports VHDL,now I think they updated to support Veriolog) because it's an unexpensive method of testing the designs of the students. For what I know this situation is common in the public university system(not sure about the private universities) of my country, is for this reason that unless the student pick up free election subjects to specialize in behavorial description or VLSI many people when finish their studies know only about VHDL as digital description language so I suppose that this propagates also to the industry.  Not sure about the situation in other European countries,although I know people from Italy, France and Germany and  they told me they did more or less the same.

Hi Jess,

I believe the choice is mostly left to the lecturer's discretion, i.e. the choice depends on his professional career path. However, I had the impression there was a "general belief" by lecturers that the move from VHDL to Verilog was easier than the other way round, reason why the preferred teaching VHDL. The decision may also be related to the fact that VHDL became an IEEE standard a long time ago, when Verilog was still proprietary.

Finally, I don't have any figures to support the following, but I wonder if Mentor Graphics used to have a larger market share in Europe compared to the Us, which might have been a reason for the success of VHDL over here too.

Paul