Hi,
I am new to Verilog-A modeling.
I've been trying to write a model for a clocked comparator, but it seems that my code has a hidden state.

`include "discipline.h"
`include "constants.h"

module comp (inp, inm, set, en, out);
input en, set, inp, inm;
output out;
electrical inp, inm, en, out, set;
parameter real vlogic_high=5,vlogic_low=0;
parameter real vtrans=(vlogic_high+vlogic_low)/2;
parameter real tdel = 2u from [0:inf);
parameter real trise = 1u from (0:inf);
parameter real tfall = 1u from (0:inf);
real out_val;
analog begin
   @(cross( V(en)-vtrans,+1 ))
   out_val = (V(inp) > V(inm)) ? vlogic_high : vlogic_low;
   V(out) <+ transition( out_val, tdel, trise, tfall);
end
endmodule

Can anybody give me some help in removing this hidden state from my model?
Many thanks,
Gabriel