Designer’s Guide Community

filipe

Junior Member

Offline

Posts: 22
Brasil

Harmonic distortion due to 1st sampling in a SDM
Aug 03^rd, 2007, 9:00am

Hi,
I'm designing a 2nd order fully differential sigma delta modulator using SC techniques, and it will be used in a 16bits ADC.
I'm having a serious problem in terms of harmonic distortion, which is around 80dB (the 2nd harmonic is -80dB, and the 3rd harmonic is -95dB).
Simulation show that the main distortion are located at the first sampling phase (when sw1a, sw1b, sw2a e sw2b are on at the figure). I conclude when the simulation is done with only the 4 sw mentioned were changed by reals switches.
The switches are complementary MOS transistors (PMOS = 6/0.6 and NMOS = 2/0.6). The lengths of the transistors are minimal. When the widths (W) of the transistors are increased, the 2nd tone does not decrease (I thought that if the Ron decreases, the 2nd harmonic should decrease too, although the non linearity is the cause).
Also, I notice that the size of the buffer (an inverter gate), that control the switches, has a big influence in the 2nd harmonic.
I tried to use dummy transistors with the switches, but the 2nd does not decrease again.
So, what could I do to reduce the harmonic distortion???
What is the influence of the logic buffer that controls the switches??? How can I choose the transistor� size of the logic buffer (gate inverter)???
The transistor dummy should be a solution???
Please, enlighten me. If one has a suggestion, or a good reference to read, tell me.
Best Regards
Filipe

Back to top

sdm.jpeg

IP Logged

HdrChopper

Community Fellow

Offline

Posts: 493

Re: Harmonic distortion due to 1st sampling in a S
Reply #1 - Aug 3^rd, 2007, 3:37pm

Hi filipe.

There are two things that make me think might be having problems with charge injection (although you are using the delayed clock signals for sampling the input signal which reduces charge injection to a first order). First, the Ron reduction did not help on reducing the 2nd harmonic power and second the influence you mentioned the logic buffer has on the 2nd harmonic component.
One thing I would try is to increase the RON (or increase the cap size) as much as you can - without compromising settling time and noise requirements - . In this the amount of charge going into the sampling cap will be smaller.
In addition, the inverter driving them should control the slope of the clock going into their gates in such a way charge injection is also minimized. This slope is a function of the switches sizes (take a look at "Dummy transistor compensation of Analog MOS switches" IEEE JSSC, Aug 1989, Eichenberger & Guggenb�hl and "On charge injection in analog MOS switches and dummy switch compensation technique" IEEE Transaction on Cricuits and Systems, Feb 1990, Eichenberger & Guggenb�hl).

Good luck
tosei

Back to top

Keep it simple

IP Logged

filipe

Junior Member

Offline

Posts: 22
Brasil

Re: Harmonic distortion due to 1st sampling in a S
Reply #2 - Aug 6^th, 2007, 10:48am

Tosei, thank a lot for your answer.
But in "A CMOS 110-dB@40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-delta Modulator for low-power high-linearity automotive sensor ASIC", JSSC 2005, (http://ieeexplore.ieee.org/iel5/4/32564/01522565.pdf?tp=&isnumber=32564&arnumber...), page 2255, first paragraph, it says that to minimize the distortion due to the first sampling, the Ron must be small.
In my project (which still has a considerable harmonic distortion) can be seen that the larger Ron, larger the distortion.
So, I'm very confusing.
Thanks!

Back to top

IP Logged

Visjnoe

Senior Member

Offline

Posts: 233

Re: Harmonic distortion due to 1st sampling in a S
Reply #3 - Aug 6^th, 2007, 11:43am

Dear all,

I haven't looked into the papers mentioned, but I would say one would first have to grasp what is actually causing this 2nd order distortion and then tweak this cause.

I find it strange to have 2nd order distortion in a differential structure, unless you've included mismatch in the simulation or there is some other imbalance I'm missing (please inform me).

Regards

Peter

Back to top

IP Logged

HdrChopper

Community Fellow

Offline

Posts: 493

Re: Harmonic distortion due to 1st sampling in a S
Reply #4 - Aug 6^th, 2007, 7:35pm

filipe wrote on Aug 6^th, 2007, 10:48am:

But in "A CMOS 110-dB@40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-delta Modulator for low-power high-linearity automotive sensor ASIC", JSSC 2005, (http://ieeexplore.ieee.org/iel5/4/32564/01522565.pdf?tp=&isnumber=32564&arnumber...), page 2255, first paragraph, it says that to minimize the distortion due to the first sampling, the Ron must be small.

Hi filipe,

I think that paper refers to the effect of non-linearity in the switch resistance being different on each side of the differential input, such difference depending on the input signal swing and thus generating harmonic distortion. In that case it is clear a smaller Ron will benefit the performance of the circuit. I just pointed out that in case your problem were related to charge injection problems, then making a larger Ron would help. Certainly that might have some drawbacks if you consider non-linearity.

As Visjnoe suggested you need some kind of circuit unbalance in order to generate such harmonic distortion, but such unbalance (you will agree with me) does not necessarily have to be a DC mismatch: it could be either non-linear Ron under input signal's large swing conditions or even charge injection (which might be different depending on the CM level for each input branch).

By the way, did you try changing the input signal's amplitude in order to see how that harmonic distortion varies (percentage wise)? that might give you a clue as to what is causing that distortion.

Regards
tosei

Back to top

Keep it simple

IP Logged

vivkr

Community Fellow

Offline

Posts: 780

Re: Harmonic distortion due to 1st sampling in a S
Reply #5 - Aug 6^th, 2007, 11:18pm

Hi Filipe,

Tosei is quite right. I would expect that your 2nd harmonic is largely owing to signal-dependent behavior in the sampling switches.
If you are willing to take the extra trouble of designing a bootstrapped switch for the input sampling network, then you might be able
to get rid of the issue altogether.

In order to locate the source of the problem exactly, I would try the following things:

1. First replace the switches by a simplified macromodel of an NMOS bootstrapped switch. This still has an NMOS device
acting as the switch, but when turned ON, the VGS is fixed regardless of the signal. You can connect an ideal voltage
source between the gate and source in the ON state with a value ~ 0.8*VDD and see if this removes your 2nd harmonic.
If yes, then bootstrapping is the way for you.

2. You can then design a bootstrapped switch. Check out the JSSC paper from M. Dessouky and A. Kaiser. I think it is JSSC, Mar. 2001.
This switch is relatively easy to realize and does not suffer from reliability issues.

You do not mention the peak signal frequency and sampling frequency of your modulator. For very high-speed inputs, you cannot achieve good
linearity unless you go to the bootstrapped switch. Note that for high frequency inputs, you will need to make both the switches of the sampling
network bootstrapped, the one connected to the input and the bottom-plate of the sampling cap, and the other one connecting the top-plate to your
common-mode.

Regards
Vivek

Back to top

IP Logged

filipe Junior Member Offline Posts: 22 Brasil	Re: Harmonic distortion due to 1st sampling in a S Reply #6 - Aug 7^th, 2007, 4:56am The SDM is supplied by 5V. The reference voltages are 1.75 and 3.25V (2.5 +- 0.75). The input signal which I'm appling has an amplitude of 1V at 5kHz, oversampling at 5MHz. Regards
Back to top	IP Logged

vivkr Community Fellow Offline Posts: 780	Re: Harmonic distortion due to 1st sampling in a S Reply #7 - Aug 7^th, 2007, 10:59pm Hi Filipe, The input frequency of 5 kHz is moderate. However, you need very good linearity at 5 MHz sampling frequency. Perhaps, it is worth trying out a simplified model for the bootstrapped switch to see if it works for you. Regards Vivek
Back to top	IP Logged