Hi

1) Is it possible in some way to simulate / observe latch up problems in Cadence occuring because of transient capacitive coupling currents i.e. Cgb, Cdb, Csb etc.
e.g. If there the normally reverse-biased diodes in the MOS transistors get forward biased, Spectre  issues a warning but there is no warning for transients currents pumped into the bulk..

2) How can I find out in my simulation setup that latch up will really occur in silicon?  (all the diodes in MOS transistors are reverse-biased)

Kind Regards,
Faisal Mateen.