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smarty Community Member Offline Posts: 46	supply noise analysis Aug 17^th, 2007, 7:43am Hi all, I have a question.. I am working on a 36 port serdes design. I am trying to estimate the supply noise because of all 36 port operating. It woudn't be possible to do a full schematic simulation and it might not also be the effective way. Can anybody suggest simpler method or model for this analysis. Best regards, SBR
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Visjnoe

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Re: supply noise analysis
Reply #1 - Aug 19^th, 2007, 1:47am

Dear Smarty,

just simulate 1 or 2 SerDes cores running simultaneously and determine the effect of supply noise.
The worst case situation is than established by extrapolating linearly to the 36-port SerDes case.
Supply noise is a form of DJ (Deterministic Jitter), this kind of jitter adds op linearly. The 'noise' you'll observe is probably due to simultaneous switching outputs or simultaneous switching circuits.

I'd have to have more insight into the real buildup of your circuit, but I'm pretty sure you can extract all the data you require from simulating 1 core.

Regards

Peter

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smarty

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Re: supply noise analysis
Reply #2 - Aug 19^th, 2007, 11:19am

Dear Peter,
Thanks for providing me an insight as to tackle this problem.

One more query to get myself clear. Since we need to do a noise and that to Switching noise, are we worried about the Ldi/dt noise (kindly correct me if I sound wrongly). We are targetting flip-chip package and from my understanding the overall inductance of the supply line should be low (since this is a flip-chip packaging).

I have thinking of 2 methods. I would be happy, if you can put your thoughts.

Method one:
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Can we do a small signal model and estimate the impedance of the supply and do an thevinins/norton, modelling the the Tx/Rx as a current source along with the supply resistance and capacitance. Then replicate this current source for 36 ports and do switching in the currnet source to estimate the noise generated at the supply.

Method two:
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As you have mentioned, do a switching of the TxRx for single and then extrapolate that for 36 ports.

For both the case, we need to model the supply and package parasitics to have the noise level.

Kindly let me know, if I have not sounded clear in my explaination.

Best Regards,
SBR

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Visjnoe

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Re: supply noise analysis
Reply #3 - Aug 20^th, 2007, 12:02am

Dear Smarty,

I think both approaches you propose are good. The first one has the benefit of a reduced simulation, but you have to make sure you model the current switching of your SerDes core accurately. It can be done however.

The second approach eases the modeling effort, but while lead to an increased simulation time (might not be dramatic however).

If you can be confident enough about the model, I would go with approach 1. Otherwise go with approach 2.
For but approaches it is indeed essential that you model the package and supply parasitics accurately.

Regards

Peter

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smarty Community Member Offline Posts: 46	Re: supply noise analysis Reply #4 - Aug 22^nd, 2007, 9:36pm Dear Peter, Thanks for the valuble inputs. We should now be able to work it out. Best Regards, SBR
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