Sirous,
I love your question, it is a very common "confused subject" in the ESD world.
"Fail Safe" ESD or I/O, as far as I am aware is really a term created by (limited to?) TI, but generally adopted by the other members of the industry, though not widely.
The idea of "Fail Safe" has almost nothing to do with ESD, rather its how the ESD impact functionality. The best example is ESD protection for an Open Drain I/O.
In open drain, the I/O driver tends to be a simple NMOS that pulls a bus line to ground. The bus generally has external pull-up resistors for pulling high, so there will be no PMOS drivers on chip, thus open drain because only the drain of the nmos is attached to the pad.. One application for this type of I/O is in a system where multiple parts will all have pins sitting on the same signal lines. However not all the parts are powered up, as some may be in power down modes.
Traditional Diode based ESD (with a diode to Vdd and a diode from VSS protect each signal pad) are problematic in this scenario. Say the bus signals, on an example bus, swing 0 to 3V. Parts A, B, and C are all on connected to the bus, but part B is powered down while A and C drive the bus. In power down mode, part B's VDD is pulled to ground, but part B also uses Diode protection for its signal pads, which are connected to the still actively driven bus lines, this diode is therefore connected to a VDD that is grounded. Every time the bus is driven high by driving +3V (in the open drain, this is accomplished by letting the bus float and pull-up res do the rest), part B loads down the signals because its ESD diode is trying to clamp the bus to a 0V VDD, son instead of 3V you get 1.2V or something, causing system failure (depending on the diode on-resistance relative to the pull-up resistors).
"Fail Safe" ESD limit this problem by creating ESD structures that are not dependent on the VDD domain. They almost never simply use a single diode as you may think, generally they are snapback devices, Grounded Gate Nmos (ggNMOS) being the most common though others such as an SCR may also be used. These structures have no parasitic diode to VDD, but at higher voltages, say 8V for our example, will trigger and clamp ESD events to the ground. In a brief nutshell that is how they work. They still can conduct positive ESD events to ground, but they do not do it by clamping it to a VDD rail that may be powered down; and thus ruin bus performance in a system with multiple power down modes and parts. They do it by setting a higher triggering point than the normal Voltage levels of the signals they are protecting.
This is "Fail Safe " ESD...ESD design that allows a part to be connected in a shared system, but does not cause the system to "fail" when it gets powered down.
I hope this helps,
Stephen
www.srftechnologies.comPS: There are ways to design "Fail Safe " ESD using Diodes, which in
most applications are far superior to snapback based devices. But thats a whole different chapter!