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Failsafe ESD protection (Read 23484 times)
sirous black
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Failsafe ESD protection
Aug 20th, 2007, 1:39am
 
Hi,

I want to know how  failsafe ESD's work.   :-?
As far as my understanding goes, failsafe is used when there are two different VDD supplies (say 5v and 3.3v). In the event that 5v supply is lost, the corresponding connected I/O's should still have ESD protection. [pls correct me if I am wrong].
I have read that failsafes use just one diode - to gnd. How does this offer ESD protection to the connected I/O?
Also, could you elucidate the differences btwn NFS and FS ? I am not looking into differential I/O's - the application is for single pad I/O.

Regards,
SB
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Re: Failsafe ESD protection
Reply #1 - Aug 21st, 2007, 6:28pm
 
Sirous,
 I love your question, it is a very common "confused subject" in the ESD world.

"Fail Safe" ESD or I/O, as far as I am aware is really a term created by (limited to?)  TI, but generally adopted by the other members of the industry, though not widely.

The idea of "Fail Safe" has almost nothing to do with ESD, rather its how the ESD impact functionality.  The best example is ESD protection for an Open Drain I/O.

In open drain, the I/O driver tends to be a simple NMOS that pulls a bus line to ground.  The bus generally has external pull-up resistors for pulling high, so there will be no PMOS drivers on chip, thus open drain because only the drain of the nmos is attached to the pad..  One application for this type of I/O is in a system where multiple parts will all have pins sitting on the same signal lines.  However not all the parts are powered up, as some may be in power down modes.

Traditional Diode based ESD (with a diode to Vdd and a diode from VSS protect each signal pad) are problematic in this scenario.  Say the bus signals, on an example bus, swing 0 to 3V.  Parts A, B, and C are all on connected to the bus, but part B is powered down while A and C drive the bus.  In power down mode, part B's VDD is pulled to ground, but part B also uses Diode protection for its signal pads, which are connected to the still actively driven bus lines, this diode is therefore connected to a VDD that is grounded.  Every time the bus is driven high by driving +3V (in the open drain, this is accomplished by letting the bus float and pull-up res do the rest), part B loads down the signals because its ESD diode is trying to clamp the bus to a 0V VDD, son instead of 3V you get 1.2V or something, causing system failure (depending on the diode on-resistance relative to the pull-up resistors).

"Fail Safe" ESD limit this problem by creating ESD structures that are not dependent on the VDD domain.  They almost never simply use a single diode as you may think, generally they are snapback devices, Grounded Gate Nmos (ggNMOS) being the most common though others such as an SCR may also be used.  These structures have no parasitic diode to VDD, but at higher voltages, say 8V for our example, will trigger and clamp ESD events to the ground.  In a brief nutshell that is how they work.  They still can conduct positive ESD events to ground, but they do not do it by clamping it to a VDD rail that may be powered down; and thus ruin bus performance in a system with multiple power down modes and parts.  They do it by setting a higher triggering point than the normal Voltage levels of the signals they are protecting.

This is "Fail Safe " ESD...ESD design that allows a part to be connected in a shared system, but does not cause the system to "fail" when it gets powered down.

I hope this helps,
Stephen
www.srftechnologies.com

PS: There are ways to design "Fail Safe " ESD using Diodes, which in most applications are far superior to snapback based devices.  But thats a whole different chapter!
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Re: Failsafe ESD protection
Reply #2 - Jul 31st, 2012, 4:15am
 
Hi Stephen,

     It was a very good explanation provided by you on the fail safe in a proper context.

      We are having a fail safe i2c pad in our chip and during the silicon testing we observed that its VIH was degrading post the following tests.

     a) I/O continuity test - injecting +ve and -ve current to test the upper and lower diode respectively for all the functional pads including the i2c pad as well. Though later the +ve current injection test on the i2c pad was removed but still degradation is there.
     b) open/short test for the power supply pads by applying a voltage of around 200mv and measuring current through each supply pad.

      It seems there is a charge accumulation on the input schmitt as
     after baking the degraded samples VIH did imprvove though could not be receovered completely.

    So my question is;
       a) Do you suspect some design weakness here?
       b) Is the ggnmos suppose to protect whenever there is a +ve charge injection into the pad or there is some other protection required? Since usually it will start conducting at and above the zener breakdown voltage how are we going to protect the pad in the case where we have a small +ve voltage on the pad while it has no VDDE e.g test b above.

regards,
AJ
     
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Re: Failsafe ESD protection
Reply #3 - Aug 27th, 2012, 11:32pm
 
Hi,

     Can any one comment on the following issue realted to the design of the fail safe io pad?

      We are having a fail safe i2c pad in our chip and during the silicon testing we observed that its VIH was degrading post the following tests.

     a) I/O continuity test - injecting +ve and -ve current to test the upper and lower diode respectively for all the functional pads including the i2c pad as well. Though later the +ve current injection test on the i2c pad was removed but still degradation is there.
     b) open/short test for the power supply pads by applying a voltage of around 200mv and measuring current through each supply pad.

      It seems there is a charge accumulation on the input schmitt as
     after baking the degraded samples VIH did imprvove though could not be receovered completely.

    So my question is;
       a) Do you suspect some design weakness here?
       b) Is the ggnmos suppose to protect whenever there is a +ve charge injection into the pad or there is some other protection required? Since usually it will start conducting at and above the zener breakdown voltage how are we going to protect the pad in the case where we have a small +ve voltage on the pad while it has no VDDE e.g test b above?

regards,
AJ
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Re: Failsafe ESD protection
Reply #4 - Sep 5th, 2012, 8:11pm
 
Hi AJ,
 So I haven't visited this forum in a long time, and on a whim decided to stop by today and saw your post.

To answer your questions:

 a) Do you suspect some design weakness here?
Hard to say, I do not know your design or the process or what the absolute values were used during testing.  All of those play a factor in answering this question.

b) Is the ggnmos suppose to protect whenever there is a +ve charge injection into the pad or there is some other protection required? Since usually it will start conducting at and above the zener breakdown voltage how are we going to protect the pad in the case where we have a small +ve voltage on the pad while it has no VDDE e.g test b above?
 
ggNMOS will only trigger above the nominal breakdown voltage of the drain, so NO, it will not necessarily protect agains low +ve levels.  Voltages that sits on the pad that is above Vmax of your IO device but below Vt1 (trigger voltage) of your ggNMOS will degrade your IO circuits.  ggNMOS are not meant to protect again small DC or AC over-voltage levels that do not exceed the Vt1 level  (i.e do not look like an ESD event).

Hope this helps.


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Re: Failsafe ESD protection
Reply #5 - Sep 5th, 2012, 11:35pm
 
Hi Stephan,

        Welcome back and Many thanks for your feedback!!

       - Yes you are right this is not an esd failure. The degradation occurred at ATE during the normal testing as I mentioned in my first post. In some tests the test engineer applied small voltages i.e 0.2v to 0.3v on the supply pads which was causing the Vih degradation as well.
       
       - During the scan test we suspect that due to ripple at the pads( i2c pads are scan inputs in atpg) during the 0 to 1 transition and at the same time we may have a dip on the io supply due to the switching current so pad voltage may be 100-200mv above the VDDE which might be causing the degradation due to the charge accumulation.

          I wanted to know what is the general practice to take care of small voltages in the fail safe ios as had the upper diode been there the io would have been safe for small voltages.
          Did you ever face such issues? May be ours is an isolated case.  :)

best regards,
AJ
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Re: Failsafe ESD protection
Reply #6 - Sep 6th, 2012, 6:13pm
 
Hi Aj,
So to be honest, there are several things I do not understand about your setup, and possibly many potential issues I see wrong with what you are doing.

First, the I2C interface is open-drain, meaning you should have external resistors pulling the signals up to your vddbus voltage.  That voltage should not be higher that what the IO is designed for and would protect against this "+ve" your mentioning.  If your testing it in an ATE env, you should be using pullups only and not driving the I2C pins.

Without truly understanding your problem as I have no idea what your design, system or test bench looks like...my best "guess" (that is what it is at this point) is that:

1. you are incorrectly testing your system because there is no reason why an open-drain output such as an I2C pin should see much overshoot, much less sustained overshoot degrading an input. (an exception being if your system voltage supply is really noisy or poorly regulated).

OR

2. Your input receiver design is inherently weak and can not tolerate the nominal voltages of the i2c interface.  (I seriously doubt you would normally see massive vih degradation simply because you get some nominal overshoot on your output, which leads me to this conclusion).

Personally I am leaning toward number 2.

Hope this helps.


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Re: Failsafe ESD protection
Reply #7 - Sep 6th, 2012, 10:33pm
 
Hi Stephan,

     When we are forcing the i2c pads they are in input mode. So you mean that even in the input mode we should not force a strong logic1 externally but should be pulled high instead. This is interesting. Could you explain this.

     You gussed it right that there is weakness in the input receiver of this io pad. As a fix, which has been validated on the ATE as well, we are going to put one 400K resistor between the pad and the ground.

      I am really thankful to you for your feedbacks.

Note:  If you have some general feedback on the fail safe ios please do share.      

regards,
Ajay
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Re: Failsafe ESD protection
Reply #8 - Sep 7th, 2012, 6:34pm
 
If you fix your receiver, than you should be fine in driving the IO during test with an active driver versus the typical bus pull-up resistors.  However make certain that your test is accurately characterizing the system env for your part if you do this.
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