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passing parameters from verilog-a to ADE (Read 3087 times)

just started New Member Offline Posts: 3 usa	passing parameters from verilog-a to ADE Aug 21^st, 2007, 9:08pm Hi I am working with a verilog-a code. I wish to be able to pass one of the parameters in that code to ADE. Maybe I am supposed to create a paramter by that name in the CDF or something... cannot find any suitable link that can help...if anyone knows please tell me...
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Geoffrey_Coram

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Re: passing parameters from verilog-a to ADE
Reply #1 - Aug 23^rd, 2007, 6:03am

just started wrote on Aug 21^st, 2007, 9:08pm:

Hi

I am working with a verilog-a code. I wish to be able to pass one of the parameters in that code to
ADE. Maybe I am supposed to create a paramter by that name in the CDF or something...
cannot find any suitable link that can help...if anyone knows please tell me...

Pass a parameter from Verilog-A to ADE? That sounds backwards. Do you mean, you want to be able to set a parameter for an instance that is modeled with Verilog-A? Creating the CDF parameter would be a good start; I don't know if your netlister needs some changes, too.

If at first you do succeed, STOP, raise your standards, and stop wasting your time.

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just started New Member Offline Posts: 3 usa	Re: passing parameters from verilog-a �to ADE Reply #2 - Aug 23^rd, 2007, 8:08am Actually I did get it...created a output voltage node in the code...passed the parameter to that node and passed that node to ADE...i wish to run monte carlo on that parameter...
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