So, nobody wants to pick up this topic?

Hey Nxing, interesting question! Would be nice to hear other people's opinion.

I am using 65nm for mixed-signal design. The square law model is pretty useless
for hand calculations of operating points etc. However, equations covering deep-submircon
effects are complicated and parameters are often unknown (and even then they might
not be accurate).

Anyway, I think when analyzing a new circuit the square law model is still good enough
to show design trade-offs and give insight how the circuit works (which can never be
achieved just using simulations). Good knowledge about
deep-submircon effects (short-channel, halo pockets etc.) is necessary should the simulation
behave different than expected . However, to finally determine the transistor dimensions I rely on
simulations.

Regards

The book

CMOS: Circuit Design, Layout, and Simulation by Jacob baker

talks about design in 65nm and less...its states that the square law does not apply and goes on to explain how to get all the necessary info about transistors using certain simulations... however as Berti and carlgrace stated..square law still works for understanding tradeoffs...though you must have sims to correctly arrive at your results... even Kn and Kp got in sims is a ball park and therefore it is an iterative process for 65 and 45nm design..

The equation you mention is actually quite well known for short-channel devices. If you get a very good match with simulation, then perhaps
it is because you have access to the required model parameters. If you find a further match between the simulations and the real circuit,
then it would also indicate that your foundry did a good job of modelling the transistors

Regards
Vivek

Square law???? Yikes! Not in many years!

A quick and dirty that works with any flavor of MOS --- run a set of bias curves using the model set. Set W/L at 1 (or 10 or whatever works for you)

Use the biase curve set to configure operating point, and do a geometry scale to get the desired current.

no math, no muss, no fuss...

that one has worked since 1960 or thereabouts, and sub-micron, short channel and all that are seen in the bias curves.

I just copy the curves published in the design manuals, paste the (screen capture or the) gif into excel, overlay a chart with transparent area then plot the "standard" equations for the I-V curves over it . I use whatever equation gives the best (or nearly good enough) fit, tweaking coefficients until I get a good fit "by eye".  I then invert the equations and "synthesize" approximately correctly sized devices to go into the netlist or schematic for simulation.  Generally these device sizes remain unchanged throughout the rest of the design process (I have only gone to 80nm so far, but the technique seems to hold up still).   I mostly used the "square law" equations with a VA and PB correction; very simple, but algebraically tractable so allowing the inversion mentioned above.  The "extraction" method generally takes a few hours for a new process, but gives a good intuitive feel for circuit behaviour even though the extracted coefficients probably bear almost no relationship to what is formally recognized as B0, Vth0 etc nor to the parameters given in PDK models.

So my comment is yes, hand calculation using the basic square law equations is still done and is still valid, even though you now have to undertake to extract the "behavioural" parameters at the point of operation of interest to you.

Just as an aside, the technique will work for almost any device, provided you choose the correct equations (ie = behavioural modelling?).  You could just as easily create a sub-circuit implementing the simple equations then tweak its parameters to a achieve a good match when compared to a sample device from the PDK, within a simulator test-bench.

Cheers, Simon2.